Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later.

compiler/bitcells/bitcell_1port.py

@@ -60,3 +60,8 @@ class bitcell_1port(bitcell_base.bitcell_base):
         Overrides base class function.
         """
         self.add_graph_edges(graph, port_nets)
+
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return False

compiler/bitcells/replica_bitcell_1port.py

@@ -48,3 +48,8 @@ class replica_bitcell_1port(bitcell_base.bitcell_base):
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges based on inputs/outputs. Overrides base class function."""
         self.add_graph_edges(graph, port_nets)
+
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return False

compiler/characterizer/delay.py

@@ -128,7 +128,7 @@ class delay(simulation):
         read_measures.append(self.create_bitline_measurement_objects())
         read_measures.append(self.create_debug_measurement_objects())
         read_measures.append(self.create_read_bit_measures())
-        #read_measures.append(self.create_sen_and_bitline_path_measures())
+        read_measures.append(self.create_sen_and_bitline_path_measures())
 
         return read_measures
 
@@ -756,6 +756,8 @@ class delay(simulation):
                 debug.error("Failed to Measure Read Port Values:\n\t\t{0}".format(read_port_dict), 1)
 
             result[port].update(read_port_dict)
+            
+            self.check_path_measures()
 
         return (True, result)
 
@@ -857,6 +859,21 @@ class delay(simulation):
         debug.info(1, "min_dicharge={}, min_diff={}".format(min_dicharge, min_diff))
         return (min_dicharge and min_diff)
 
+    def check_path_measures(self):
+        """Get and check all the delays along the sen and bitline paths"""
+        
+        # Get and set measurement, no error checking done other than prints.
+        debug.info(2, "Checking measures in Delay Path")
+        value_dict = {}
+        for meas in self.sen_path_meas+self.bl_path_meas:
+            val = meas.retrieve_measure()
+            debug.info(2, '{}={}'.format(meas.name, val))
+            if type(val) != float or val > self.period/2:
+                debug.info(1,'Failed measurement:{}={}'.format(meas.name, val))
+            value_dict[meas.name] = val
+        
+        return value_dict
+
     def run_power_simulation(self):
         """
         This simulates a disabled SRAM to get the leakage power when it is off.

compiler/custom/sense_amp.py

@@ -73,3 +73,9 @@ class sense_amp(design.design):
     def build_graph(self, graph, inst_name, port_nets):
         """Adds edges based on inputs/outputs. Overrides base class function."""
         self.add_graph_edges(graph, port_nets)
+        
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        #FIXME: This only applied to bl/br -> dout and not s_en->dout
+        return True     

compiler/pgates/pand2.py

@@ -146,3 +146,8 @@ class pand2(pgate.pgate):
                                             offset=pin.center(),
                                             width=pin.width(),
                                             height=pin.height())
+    
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return True

compiler/pgates/pinv.py

@@ -337,3 +337,8 @@ class pinv(pgate.pgate):
         Overrides base class function.
         """
         self.add_graph_edges(graph, port_nets)
+        
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return False    

compiler/pgates/pnand2.py

@@ -314,3 +314,8 @@ class pnand2(pgate.pgate):
         Overrides base class function.
         """
         self.add_graph_edges(graph, port_nets)
+
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return False

compiler/pgates/pnand3.py

@@ -347,3 +347,8 @@ class pnand3(pgate.pgate):
         Overrides base class function.
         """
         self.add_graph_edges(graph, port_nets)
+
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+        
+        return False