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Names in skiptests changed. Reduce grid router verbosity.

This commit is contained in:
mrg 2020-10-23 09:22:59 -07:00
parent dcd29214bc
commit cbf9c48504
3 changed files with 18 additions and 20 deletions
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14
compiler/router/pin_group.py
View File

@ -552,7 +552,7 @@ class pin_group:
Add the enclosure shape to the given cell.
"""
for enclosure in self.enclosures:
debug.info(2, "Adding enclosure {0} {1}".format(self.name,
debug.info(4, "Adding enclosure {0} {1}".format(self.name,
enclosure))
cell.add_rect(layer=enclosure.layer,
offset=enclosure.ll(),
@ -612,7 +612,7 @@ class pin_group:
blockage_set = set()
for pin in self.pins:
debug.info(2, " Converting {0}".format(pin))
debug.info(4, " Converting {0}".format(pin))
# Determine which tracks the pin overlaps
(sufficient, insufficient) = self.router.convert_pin_to_tracks(self.name,
pin)
@ -628,15 +628,15 @@ class pin_group:
# Remember, this excludes the pin blockages already
shared_set = pin_set & self.router.blocked_grids
if len(shared_set) > 0:
debug.info(2, "Removing pins {}".format(shared_set))
debug.info(4, "Removing pins {}".format(shared_set))
pin_set.difference_update(shared_set)
shared_set = partial_set & self.router.blocked_grids
if len(shared_set) > 0:
debug.info(2, "Removing pins {}".format(shared_set))
debug.info(4, "Removing pins {}".format(shared_set))
partial_set.difference_update(shared_set)
shared_set = blockage_set & self.router.blocked_grids
if len(shared_set) > 0:
debug.info(2, "Removing blocks {}".format(shared_set))
debug.info(4, "Removing blocks {}".format(shared_set))
blockage_set.difference_update(shared_set)
# At least one of the groups must have some valid tracks
@ -666,5 +666,5 @@ class pin_group:
# Remember the secondary grids for removing adjacent pins
self.secondary_grids = partial_set
debug.info(2, " pins {}".format(self.grids))
debug.info(2, " secondary {}".format(self.secondary_grids))
debug.info(4, " pins {}".format(self.grids))
debug.info(4, " secondary {}".format(self.secondary_grids))

20
compiler/router/router.py
View File

@ -301,7 +301,6 @@ class router(router_tech):
adj_grids))
self.remove_adjacent_grid(pg1, pg2, adj_grids)
debug.info(1, "Removed {} adjacent grids.".format(removed_grids))
def remove_adjacent_grid(self, pg1, pg2, adj_grids):
@ -539,7 +538,7 @@ class router(router_tech):
sufficient_list.update([full_overlap])
if partial_overlap:
insufficient_list.update([partial_overlap])
debug.info(2,
debug.info(3,
"Converting [ {0} , {1} ] full={2}".format(x,
y,
full_overlap))
@ -632,26 +631,26 @@ class router(router_tech):
pin.layer)
overlap_length = pin.overlap_length(track_pin)
debug.info(2,"Check overlap: {0} {1} . {2} = {3}".format(coord,
debug.info(4,"Check overlap: {0} {1} . {2} = {3}".format(coord,
pin.rect,
track_pin,
overlap_length))
inflated_overlap_length = inflated_pin.overlap_length(track_pin)
debug.info(2,"Check overlap: {0} {1} . {2} = {3}".format(coord,
debug.info(4,"Check overlap: {0} {1} . {2} = {3}".format(coord,
inflated_pin.rect,
track_pin,
inflated_overlap_length))
# If it overlaps with the pin, it is sufficient
if overlap_length == math.inf or overlap_length > 0:
debug.info(2," Overlap: {0} >? {1}".format(overlap_length, 0))
debug.info(4," Overlap: {0} >? {1}".format(overlap_length, 0))
return (coord, None)
# If it overlaps with the inflated pin, it is partial
elif inflated_overlap_length == math.inf or inflated_overlap_length > 0:
debug.info(2," Partial overlap: {0} >? {1}".format(inflated_overlap_length, 0))
debug.info(4," Partial overlap: {0} >? {1}".format(inflated_overlap_length, 0))
return (None, coord)
else:
debug.info(2, " No overlap: {0} {1}".format(overlap_length, 0))
debug.info(4, " No overlap: {0} {1}".format(overlap_length, 0))
return (None, None)
def convert_track_to_pin(self, track):
@ -846,7 +845,7 @@ class router(router_tech):
"Pin component index too large.")
pin_in_tracks = self.pin_groups[pin_name][index].grids
debug.info(2,"Set source: " + str(pin_name) + " " + str(pin_in_tracks))
debug.info(3,"Set source: " + str(pin_name) + " " + str(pin_in_tracks))
self.rg.add_source(pin_in_tracks)
def add_path_target(self, paths):
@ -914,7 +913,7 @@ class router(router_tech):
"""
path = self.prepare_path(path)
debug.info(2, "Adding route: {}".format(str(path)))
debug.info(4, "Adding route: {}".format(str(path)))
# If it is only a square, add an enclosure to the track
if len(path) == 1:
self.add_single_enclosure(path[0][0])
@ -1007,8 +1006,7 @@ class router(router_tech):
# returns the path in tracks
(path, cost) = self.rg.route(detour_scale)
if path:
debug.info(1, "Found path: cost={0} ".format(cost))
debug.info(1, str(path))
debug.info(2, "Found path: cost={0} {1}".format(cost, str(path)))
self.paths.append(path)
self.add_route(path)

4
compiler/tests/skip_tests_sky130.txt
View File

@ -2,7 +2,7 @@
04_pbitcell_test.py
04_precharge_pbitcell_test.py
04_replica_pbitcell_test.py
04_single_level_column_mux_pbitcell_test.py
04_column_mux_pbitcell_test.py
05_bitcell_1rw_1r_array_test.py
05_bitcell_array_test.py
05_dummy_array_test.py
@ -14,7 +14,7 @@
06_hierarchical_predecode3x8_pbitcell_test.py
06_hierarchical_predecode3x8_test.py
06_hierarchical_predecode4x16_test.py
07_single_level_column_mux_array_pbitcell_test.py
07_column_mux_array_pbitcell_test.py
08_wordline_driver_array_pbitcell_test.py
08_wordline_driver_array_test.py
09_sense_amp_array_test_pbitcell.py