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Fix errors in new run_sim calls and corners

This commit is contained in:
mrg 2020-11-09 13:59:46 -08:00
parent e31cbeaa6f
commit 0ba2feee53
13 changed files with 13 additions and 20 deletions
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2
compiler/characterizer/delay.py
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@ -782,7 +782,7 @@ class delay(simulation):
# sys.exit(1)
self.write_power_stimulus(trim=True)
self.stim.run_sim()
self.stim.run_sim(self.power_stim_sp)
trim_leakage_power=parse_spice_list("timing", "leakage_power")
debug.check(trim_leakage_power!="Failed", "Could not measure leakage power.")
debug.info(1, "Leakage power of trimmed array is {0} mW".format(trim_leakage_power * 1e3))

2
compiler/characterizer/setup_hold.py
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@ -218,7 +218,7 @@ class setup_hold():
infeasible_bound,
feasible_bound))
self.stim.run_sim()
self.stim.run_sim(self.stim_sp)
clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time"))
if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q) and type(setuphold_time)==float:

2
compiler/globals.py
View File

@ -469,7 +469,7 @@ def set_default_corner():
if OPTS.nominal_corner_only:
OPTS.process_corners = ["TT"]
else:
OPTS.process_corners = tech.spice["fet_models"].keys()
OPTS.process_corners = list(tech.spice["fet_models"].keys())
if (OPTS.supply_voltages == ""):
if OPTS.nominal_corner_only:

3
compiler/tests/22_sram_1bank_4mux_func_test.py
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@ -46,8 +46,7 @@ class sram_1bank_4mux_func_test(openram_test):
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, tempspice)
(fail, error) = f.run()
self.assertTrue(fail, error)

3
compiler/tests/22_sram_1bank_8mux_func_test.py
View File

@ -49,8 +49,7 @@ class sram_1bank_8mux_func_test(openram_test):
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, tempspice)
(fail, error) = f.run()
self.assertTrue(fail, error)

3
compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
View File

@ -49,8 +49,7 @@ class psram_1bank_nomux_func_test(openram_test):
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, tempspice)
(fail, error) = f.run()
self.assertTrue(fail, error)

3
compiler/tests/22_sram_1bank_nomux_func_test.py
View File

@ -45,8 +45,7 @@ class sram_1bank_nomux_func_test(openram_test):
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, tempspice)
(fail, error) = f.run()
self.assertTrue(fail, error)

3
compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py
View File

@ -46,8 +46,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test):
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, tempspice)
(fail, error) = f.run()
self.assertTrue(fail, error)

3
compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
View File

@ -52,8 +52,7 @@ class sram_wmask_1w_1r_func_test(openram_test):
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, tempspice)
(fail, error) = f.run()
self.assertTrue(fail, error)

3
compiler/tests/22_sram_wmask_func_test.py
View File

@ -48,8 +48,7 @@ class sram_wmask_func_test(openram_test):
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f = functional(s.s, tempspice)
(fail, error) = f.run()
self.assertTrue(fail, error)

2
compiler/tests/26_hspice_pex_pinv_test.py
View File

@ -77,7 +77,7 @@ class hspice_pex_pinv_test(openram_test):
sim_file = OPTS.openram_temp + "stim.sp"
log_file_name = "timing"
test_sim = self.write_simulation(sim_file, test_module, top_level_name)
test_sim.run_sim()
test_sim.run_sim("stim.sp")
delay = parse_spice_list(log_file_name, "pinv_delay")
return delay

2
compiler/tests/26_ngspice_pex_pinv_test.py
View File

@ -76,7 +76,7 @@ class ngspice_pex_pinv_test(openram_test):
sim_file = OPTS.openram_temp + "stim.sp"
log_file_name = "timing"
test_sim = self.write_simulation(sim_file, test_module, top_level_name)
test_sim.run_sim()
test_sim.run_sim("stim.sp")
delay = parse_spice_list(log_file_name, "pinv_delay")
return delay

2
compiler/verify/__init__.py
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@ -40,7 +40,7 @@ else:
OPTS.magic_exe = get_tool("GDS", ["magic"])
if not OPTS.drc_exe:
from .none import run_drc, print_drc_stats
from .none import run_drc, print_drc_stats, write_drc_script
elif "calibre"==OPTS.drc_exe[0]:
from .calibre import run_drc, print_drc_stats, write_drc_script
elif "assura"==OPTS.drc_exe[0]: