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Use bitcell_base for all bitcells. Fix missing setup_bitcell call

This commit is contained in:
mrg 2020-11-02 17:00:15 -08:00
parent fa89b73ef8
commit f9787eb878
12 changed files with 39 additions and 37 deletions
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1
compiler/base/utils.py
View File

@ -78,6 +78,7 @@ def auto_measure_libcell(pin_list, name, units, lpp):
_GDS_READER_CACHE = {}
def _get_gds_reader(units, gds_filename):
gds_absname = os.path.realpath(gds_filename)
k = (units, gds_absname)

2
compiler/bitcells/bitcell.py
View File

@ -30,7 +30,7 @@ class bitcell(bitcell_base.bitcell_base):
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
super().__init__(name, cell_name)
debug.info(2, "Create bitcell")
self.nets_match = self.do_nets_exist(self.storage_nets)

2
compiler/bitcells/bitcell_1rw_1r.py
View File

@ -34,7 +34,7 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base):
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
super().__init__(name, cell_name)
debug.info(2, "Create bitcell with 1RW and 1R Port")
self.nets_match = self.do_nets_exist(self.storage_nets)

2
compiler/bitcells/bitcell_1w_1r.py
View File

@ -34,7 +34,7 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
def __init__(self, name, cell_name):
if not cell_name:
cell_name = OPTS.bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
super().__init__(self, name, cell_name)
debug.info(2, "Create bitcell with 1W and 1R Port")
self.nets_match = self.do_nets_exist(self.storage_nets)

2
compiler/bitcells/dummy_bitcell.py
View File

@ -28,7 +28,7 @@ class dummy_bitcell(bitcell_base.bitcell_base):
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
super().__init__(name, cell_name)
debug.info(2, "Create dummy bitcell")

2
compiler/bitcells/dummy_bitcell_1rw_1r.py
View File

@ -32,7 +32,7 @@ class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
super().__init__(name, cell_name)
debug.info(2, "Create dummy bitcell 1rw+1r object")

2
compiler/bitcells/dummy_bitcell_1w_1r.py
View File

@ -32,7 +32,7 @@ class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.dummy_bitcell_name
bitcell_base.bitcell_base.__init__(self, name, cell_name)
super().__init__(name, cell_name)
debug.info(2, "Create dummy bitcell 1w+1r object")

15
compiler/bitcells/replica_bitcell.py
View File

@ -5,15 +5,15 @@
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import design
import debug
import utils
import bitcell_base
from tech import GDS, layer
from tech import cell_properties as props
from globals import OPTS
class replica_bitcell(design.design):
class replica_bitcell(bitcell_base.bitcell_base):
"""
A single bit cell (6T, 8T, etc.)
This module implements the single memory cell used in the design. It
@ -26,23 +26,14 @@ class replica_bitcell(design.design):
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
cell_size_layer = "boundary"
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
# Ignore the name argument
design.design.__init__(self, name, cell_name)
super().__init__(name, cell_name)
debug.info(2, "Create replica bitcell object")
(self.width, self.height) = utils.get_libcell_size(cell_name,
GDS["unit"],
layer[self.cell_size_layer])
self.pin_map = utils.get_libcell_pins(self.pin_names,
cell_name,
GDS["unit"])
def get_stage_effort(self, load):
parasitic_delay = 1
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node

10
compiler/bitcells/replica_bitcell_1rw_1r.py
View File

@ -5,13 +5,15 @@
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import design
import debug
import bitcell_base
from tech import cell_properties as props
from tech import GDS, layer
from globals import OPTS
import utils
class replica_bitcell_1rw_1r(design.design):
class replica_bitcell_1rw_1r(bitcell_base):
"""
A single bit cell which is forced to store a 0.
This module implements the single memory cell used in the design. It
@ -27,11 +29,11 @@ class replica_bitcell_1rw_1r(design.design):
props.bitcell.cell_1rw1r.pin.vdd,
props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
design.design.__init__(self, name, cell_name)
super().__init__(name, cell_name)
debug.info(2, "Create replica bitcell 1rw+1r object")
def get_stage_effort(self, load):

11
compiler/bitcells/replica_bitcell_1w_1r.py
View File

@ -5,13 +5,15 @@
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import design
import debug
import bitcell_base
from tech import cell_properties as props
from globals import OPTS
from tech import GDS, layer
import utils
class replica_bitcell_1w_1r(design.design):
class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
"""
A single bit cell which is forced to store a 0.
This module implements the single memory cell used in the design. It
@ -27,13 +29,14 @@ class replica_bitcell_1w_1r(design.design):
props.bitcell.cell_1w1r.pin.vdd,
props.bitcell.cell_1w1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = OPTS.replica_bitcell_name
design.design.__init__(self, name, cell_name)
super().__init__(name, cell_name)
debug.info(2, "Create replica bitcell 1w+1r object")
def get_stage_effort(self, load):
parasitic_delay = 1
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node

16
compiler/globals.py
View File

@ -189,9 +189,9 @@ def init_openram(config_file, is_unit_test=True):
OPTS.__dict__ = CHECKPOINT_OPTS.__dict__.copy()
return
# Setup the correct bitcell names
# Setup correct bitcell names
setup_bitcell()
# Import these to find the executables for checkpointing
import characterizer
import verify
@ -213,10 +213,6 @@ def setup_bitcell():
if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0):
OPTS.bitcell = "bitcell"
OPTS.bitcell_name = "cell_6t"
OPTS.replica_bitcell = "replica_bitcell"
OPTS.replica_bitcell_name = "replica_cell_6t"
OPTS.dummy_bitcell = "dummy_bitcell"
OPTS.dummy_bitcell_name = "dummy_cell_6t"
else:
ports = ""
if OPTS.num_rw_ports > 0:
@ -230,7 +226,13 @@ def setup_bitcell():
OPTS.bitcell_suffix = "_" + ports
OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix
OPTS.bitcell_name = "cell" + OPTS.bitcell_suffix
OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell
OPTS.dummy_bitcell_name = "dummy_" + OPTS.bitcell_name
OPTS.replica_bitcell = "replica_" + OPTS.bitcell
OPTS.replica_bitcell_name = "replica_" + OPTS.bitcell_name
# See if bitcell exists
try:
__import__(OPTS.bitcell)

11
compiler/tests/14_replica_column_test.py
View File

@ -6,28 +6,31 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class replica_column_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing replica column for 6t_cell")
debug.info(2, "Testing replica column for cell_6t")
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1)
self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell")
debug.info(2, "Testing replica column for cell_1rw_1r")
globals.setup_bitcell()
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell")
debug.info(2, "Testing replica column for cell_1rw_1r")
globals.setup_bitcell()
a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2)
self.local_check(a)