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Remove split_wl

This commit is contained in:
mrg 2020-10-12 17:27:20 -07:00
parent ca2ce8b070
commit fcb7f42e48
5 changed files with 28 additions and 63 deletions
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8
compiler/base/custom_cell_properties.py
View File

@ -32,9 +32,8 @@ class _mirror_axis:
self.y = y
class _bitcell:
def __init__(self, mirror, split_wl, cell_s8_6t, cell_6t, cell_1rw1r, cell_1w1r):
def __init__(self, mirror, cell_s8_6t, cell_6t, cell_1rw1r, cell_1w1r):
self.mirror = mirror
self.split_wl = split_wl
self._s8_6t = cell_s8_6t
self._6t = cell_6t
self._1rw1r = cell_1rw1r
@ -43,8 +42,8 @@ class _bitcell:
def _default():
axis = _mirror_axis(True, False)
cell_s8_6t = _cell({'bl' : 'bl0',
'br' : 'bl1',
cell_s8_6t = _cell({'bl' : 'bl',
'br' : 'br',
'wl': 'wl'})
cell_6t = _cell({'bl' : 'bl',
@ -69,7 +68,6 @@ class _bitcell:
cell_6t=cell_6t,
cell_1rw1r=cell_1rw1r,
cell_1w1r=cell_1w1r,
split_wl = [],
mirror=axis)
@property

29
compiler/bitcells/bitcell.py
View File

@ -22,17 +22,12 @@ class bitcell(bitcell_base.bitcell_base):
# If we have a split WL bitcell, if not be backwards
# compatible in the tech file
if props.compare_ports(props.bitcell.split_wl):
pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
else:
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
(width, height) = utils.get_libcell_size("cell_6t",
@ -55,10 +50,7 @@ class bitcell(bitcell_base.bitcell_base):
def get_all_wl_names(self):
""" Creates a list of all wordline pin names """
if props.compare_ports(props.bitcell.split_wl):
row_pins = ["wl0", "wl1"]
else:
row_pins = [props.bitcell.cell_6t.pin.wl]
row_pins = [props.bitcell.cell_6t.pin.wl]
return row_pins
def get_all_bitline_names(self):
@ -87,11 +79,8 @@ class bitcell(bitcell_base.bitcell_base):
def get_wl_name(self, port=0):
"""Get wl name"""
if props.compare_ports(props.bitcell.split_wl):
return "wl{}".format(port)
else:
debug.check(port == 0, "One port for bitcell only.")
return props.bitcell.cell_6t.pin.wl
debug.check(port == 0, "One port for bitcell only.")
return props.bitcell.cell_6t.pin.wl
def build_graph(self, graph, inst_name, port_nets):
"""

17
compiler/bitcells/replica_bitcell.py
View File

@ -20,17 +20,12 @@ class replica_bitcell(design.design):
is a hand-made cell, so the layout and netlist should be available in
the technology library. """
if cell_properties.compare_ports(cell_properties.bitcell.split_wl):
pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
else:
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
if not OPTS.netlist_only:
(width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"])

31
compiler/custom/s8_bitcell.py
View File

@ -20,19 +20,12 @@ class s8_bitcell(bitcell_base.bitcell_base):
library.
"""
# If we have a split WL bitcell, if not be backwards
# compatible in the tech file
if props.compare_ports(props.bitcell.split_wl):
pin_names = ["bl0", "bl1", "wl0", "wl1", "vpwr", "vgnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
else:
pin_names = [props.bitcell.cell_s8_6t.pin.bl,
props.bitcell.cell_s8_6t.pin.br,
props.bitcell.cell_s8_6t.pin.wl,
"vpwr",
"vgnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
pin_names = [props.bitcell.cell_s8_6t.pin.bl,
props.bitcell.cell_s8_6t.pin.br,
props.bitcell.cell_s8_6t.pin.wl,
"vpwr",
"vgnd"]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar']
def __init__(self, version="opt1", name=""):
@ -57,10 +50,7 @@ class s8_bitcell(bitcell_base.bitcell_base):
def get_all_wl_names(self):
""" Creates a list of all wordline pin names """
if props.compare_ports(props.bitcell.split_wl):
row_pins = ["wl0", "wl1"]
else:
row_pins = [props.bitcell.cell_s8_6t.pin.wl]
row_pins = [props.bitcell.cell_s8_6t.pin.wl]
return row_pins
def get_all_bitline_names(self):
@ -89,11 +79,8 @@ class s8_bitcell(bitcell_base.bitcell_base):
def get_wl_name(self, port=0):
"""Get wl name"""
if props.compare_ports(props.bitcell.split_wl):
return "wl{}".format(port)
else:
debug.check(port == 0, "One port for bitcell only.")
return props.bitcell.cell_s8_6t.pin.wl
debug.check(port == 0, "One port for bitcell only.")
return props.bitcell.cell_s8_6t.pin.wl
def build_graph(self, graph, inst_name, port_nets):
"""

6
compiler/modules/bitcell_base_array.py
View File

@ -59,11 +59,7 @@ class bitcell_base_array(design.design):
def create_all_wordline_names(self, remove_num_wordlines=0):
for row in range(self.row_size - remove_num_wordlines):
for port in self.all_ports:
if not cell_properties.compare_ports(cell_properties.bitcell.split_wl):
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
else:
self.wordline_names[port].append("wl0_{0}_{1}".format(port, row))
self.wordline_names[port].append("wl1_{0}_{1}".format(port, row))
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]