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Small fix for finding pin names in timing graph.

This commit is contained in:
mrg 2020-11-16 13:57:31 -08:00
parent 86799ae3ff
commit 902b92223f
3 changed files with 3 additions and 3 deletions
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2
compiler/bitcells/bitcell_2port.py
View File

@ -91,7 +91,7 @@ class bitcell_2port(bitcell_base.bitcell_base):
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph. Multiport bitcell timing graph is too complex
to use the add_graph_edges function."""
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)}
# Edges hardcoded here. Essentially wl->bl/br for both ports.
# Port 0 edges
graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)

2
compiler/bitcells/replica_bitcell_2port.py
View File

@ -41,7 +41,7 @@ class replica_bitcell_2port(bitcell_base.bitcell_base):
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph. Multiport bitcell timing graph is too complex
to use the add_graph_edges function."""
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)}
# Edges hardcoded here. Essentially wl->bl/br for both ports.
# Port 0 edges
graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)

2
compiler/custom/sense_amp.py
View File

@ -67,7 +67,7 @@ class sense_amp(design.design):
"""Returns name used for enable net"""
# FIXME: A better programmatic solution to designate pins
enable_name = self.en_name
debug.check(enable_name in self.pins, "Enable name {} not found in pin list".format(enable_name))
debug.check(enable_name in self.pin_names, "Enable name {} not found in pin list".format(enable_name))
return enable_name
def build_graph(self, graph, inst_name, port_nets):