Fix base class error

This commit is contained in:
mrg 2020-11-02 17:41:14 -08:00
parent f9787eb878
commit aec5865d71
1 changed files with 1 additions and 3 deletions

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@ -8,12 +8,10 @@
import debug
import bitcell_base
from tech import cell_properties as props
from tech import GDS, layer
from globals import OPTS
import utils
class replica_bitcell_1rw_1r(bitcell_base):
class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
"""
A single bit cell which is forced to store a 0.
This module implements the single memory cell used in the design. It