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Merge branch 's8_single_port' into dev

This commit is contained in:
mrg 2020-11-18 13:59:43 -08:00
parent 6cfa20731c 50a0b88ef8
commit 8507881ea8
1 changed files with 7 additions and 1 deletions
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8
compiler/base/design.py
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@ -26,8 +26,14 @@ class design(hierarchy_design):
# This allows us to use different GDS/spice circuits for hard cells instead of the default ones
# Except bitcell names are generated automatically by the globals.py setup_bitcells routines
# depending on the number of ports.
if name in props.names:
cell_name = props.names[name]
if isinstance(name , list):
num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
cell_name = props.names[name][num_ports]
else:
cell_name = props.name[name]
elif not cell_name:
cell_name = name
super().__init__(name, cell_name)