mirror of https://github.com/VLSIDA/OpenRAM.git
Allow overriding the cell size layer name.
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232f754c73
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@ -35,6 +35,8 @@ class bitcell(bitcell_base.bitcell_base):
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type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
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storage_nets = ['Q', 'Q_bar']
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cell_size_layer = "boundary"
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def __init__(self, name=""):
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if not name:
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name = self.name
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@ -44,7 +46,7 @@ class bitcell(bitcell_base.bitcell_base):
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(width, height) = utils.get_libcell_size(name,
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GDS["unit"],
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layer["boundary"])
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layer[self.cell_size_layer])
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pin_map = utils.get_libcell_pins(self.pin_names,
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name,
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GDS["unit"])
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