mirror of https://github.com/VLSIDA/OpenRAM.git
Convert design class data to static
This commit is contained in:
mrg
parent
f23fe07893
commit
07ef43eaf8
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@ -8,6 +8,7 @@
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from hierarchy_design import hierarchy_design
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from utils import round_to_grid
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import contact
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from tech import preferred_directions
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from globals import OPTS
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import re
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@ -18,21 +19,108 @@ class design(hierarchy_design):
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some DRC/layer constants and analytical models for other modules to reuse.
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"""
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def __init__(self, name):
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super().__init__(name)
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self.setup_drc_constants()
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self.setup_layer_constants()
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self.setup_multiport_constants()
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def check_pins(self):
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for pin_name in self.pins:
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pins = self.get_pins(pin_name)
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for pin in pins:
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print(pin_name, pin)
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@classmethod
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def setup_drc_constants(design):
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"""
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These are some DRC constants used in many places
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in the compiler.
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"""
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# Make some local rules for convenience
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from tech import drc
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for rule in drc.keys():
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# Single layer width rules
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match = re.search(r"minwidth_(.*)", rule)
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if match:
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if match.group(1) == "active_contact":
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setattr(design, "contact_width", drc(match.group(0)))
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else:
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setattr(design, match.group(1) + "_width", drc(match.group(0)))
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# Single layer area rules
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match = re.search(r"minarea_(.*)", rule)
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if match:
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setattr(design, match.group(0), drc(match.group(0)))
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# Single layer spacing rules
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match = re.search(r"(.*)_to_(.*)", rule)
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if match and match.group(1) == match.group(2):
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setattr(design, match.group(1) + "_space", drc(match.group(0)))
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elif match and match.group(1) != match.group(2):
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if match.group(2) == "poly_active":
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setattr(design, match.group(1) + "_to_contact",
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drc(match.group(0)))
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else:
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setattr(design, match.group(0), drc(match.group(0)))
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match = re.search(r"(.*)_enclose_(.*)", rule)
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if match:
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setattr(design, match.group(0), drc(match.group(0)))
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match = re.search(r"(.*)_extend_(.*)", rule)
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if match:
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setattr(design, match.group(0), drc(match.group(0)))
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# Create the maximum well extend active that gets used
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# by cells to extend the wells for interaction with other cells
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from tech import layer
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design.well_extend_active = 0
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if "nwell" in layer:
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design.well_extend_active = max(design.well_extend_active, design.nwell_extend_active)
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if "pwell" in layer:
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design.well_extend_active = max(design.well_extend_active, design.pwell_extend_active)
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# The active offset is due to the well extension
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if "pwell" in layer:
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design.pwell_enclose_active = drc("pwell_enclose_active")
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else:
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design.pwell_enclose_active = 0
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if "nwell" in layer:
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design.nwell_enclose_active = drc("nwell_enclose_active")
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else:
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design.nwell_enclose_active = 0
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# Use the max of either so that the poly gates will align properly
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design.well_enclose_active = max(design.pwell_enclose_active,
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design.nwell_enclose_active,
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design.active_space)
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def setup_layer_constants(self):
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# These are for debugging previous manual rules
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if False:
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print("poly_width", design.poly_width)
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print("poly_space", design.poly_space)
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print("m1_width", design.m1_width)
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print("m1_space", design.m1_space)
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print("m2_width", design.m2_width)
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print("m2_space", design.m2_space)
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print("m3_width", design.m3_width)
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print("m3_space", design.m3_space)
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print("m4_width", design.m4_width)
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print("m4_space", design.m4_space)
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print("active_width", design.active_width)
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print("active_space", design.active_space)
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print("contact_width", design.contact_width)
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print("poly_to_active", design.poly_to_active)
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print("poly_extend_active", design.poly_extend_active)
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print("poly_to_contact", design.poly_to_contact)
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print("active_contact_to_gate", design.active_contact_to_gate)
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print("poly_contact_to_gate", design.poly_contact_to_gate)
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print("well_enclose_active", design.well_enclose_active)
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print("implant_enclose_active", design.implant_enclose_active)
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print("implant_space", design.implant_space)
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import sys
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sys.exit(1)
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@classmethod
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def setup_layer_constants(design):
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"""
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These are some layer constants used
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in many places in the compiler.
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@ -46,7 +134,7 @@ class design(hierarchy_design):
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# Set the stack as a local helper
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try:
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layer_stack = getattr(tech, key)
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setattr(self, key, layer_stack)
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setattr(design, key, layer_stack)
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except AttributeError:
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pass
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@ -55,14 +143,14 @@ class design(hierarchy_design):
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continue
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# Add the pitch
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setattr(self,
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setattr(design,
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"{}_pitch".format(layer),
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self.compute_pitch(layer, True))
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design.compute_pitch(layer, True))
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# Add the non-preferrd pitch (which has vias in the "wrong" way)
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setattr(self,
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setattr(design,
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"{}_nonpref_pitch".format(layer),
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self.compute_pitch(layer, False))
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design.compute_pitch(layer, False))
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if False:
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from tech import preferred_directions
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@ -73,17 +161,18 @@ class design(hierarchy_design):
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continue
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try:
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print("{0} width {1} space {2}".format(name,
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getattr(self, "{}_width".format(name)),
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getattr(self, "{}_space".format(name))))
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getattr(design, "{}_width".format(name)),
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getattr(design, "{}_space".format(name))))
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print("pitch {0} nonpref {1}".format(getattr(self, "{}_pitch".format(name)),
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getattr(self, "{}_nonpref_pitch".format(name))))
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print("pitch {0} nonpref {1}".format(getattr(design, "{}_pitch".format(name)),
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getattr(design, "{}_nonpref_pitch".format(name))))
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except AttributeError:
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pass
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import sys
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sys.exit(1)
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def compute_pitch(self, layer, preferred=True):
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@staticmethod
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def compute_pitch(layer, preferred=True):
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"""
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This is the preferred direction pitch
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@ -95,13 +184,18 @@ class design(hierarchy_design):
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for stack in layer_stacks:
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# Compute the pitch with both vias above and below (if they exist)
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if stack[0] == layer:
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pitches.append(self.compute_layer_pitch(stack, preferred))
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pitches.append(design.compute_layer_pitch(stack, preferred))
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if stack[2] == layer:
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pitches.append(self.compute_layer_pitch(stack[::-1], True))
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pitches.append(design.compute_layer_pitch(stack[::-1], True))
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return max(pitches)
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def compute_layer_pitch(self, layer_stack, preferred):
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@staticmethod
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def get_preferred_direction(layer):
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return preferred_directions[layer]
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@staticmethod
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def compute_layer_pitch(layer_stack, preferred):
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(layer1, via, layer2) = layer_stack
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try:
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@ -113,113 +207,26 @@ class design(hierarchy_design):
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contact1 = getattr(contact, layer2 + "_via")
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if preferred:
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if self.get_preferred_direction(layer1) == "V":
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if preferred_directions[layer1] == "V":
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contact_width = contact1.first_layer_width
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else:
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contact_width = contact1.first_layer_height
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else:
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if self.get_preferred_direction(layer1) == "V":
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if preferred_directions[layer1] == "V":
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contact_width = contact1.first_layer_height
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else:
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contact_width = contact1.first_layer_width
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layer_space = getattr(self, layer1 + "_space")
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layer_space = getattr(design, layer1 + "_space")
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#print(layer_stack)
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#print(contact1)
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pitch = contact_width + layer_space
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return round_to_grid(pitch)
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def setup_drc_constants(self):
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"""
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These are some DRC constants used in many places
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in the compiler.
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"""
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# Make some local rules for convenience
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from tech import drc
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for rule in drc.keys():
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# Single layer width rules
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match = re.search(r"minwidth_(.*)", rule)
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if match:
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if match.group(1) == "active_contact":
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setattr(self, "contact_width", drc(match.group(0)))
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else:
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setattr(self, match.group(1) + "_width", drc(match.group(0)))
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# Single layer area rules
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match = re.search(r"minarea_(.*)", rule)
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if match:
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setattr(self, match.group(0), drc(match.group(0)))
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# Single layer spacing rules
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match = re.search(r"(.*)_to_(.*)", rule)
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if match and match.group(1) == match.group(2):
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setattr(self, match.group(1) + "_space", drc(match.group(0)))
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elif match and match.group(1) != match.group(2):
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if match.group(2) == "poly_active":
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setattr(self, match.group(1) + "_to_contact",
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drc(match.group(0)))
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else:
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setattr(self, match.group(0), drc(match.group(0)))
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match = re.search(r"(.*)_enclose_(.*)", rule)
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if match:
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setattr(self, match.group(0), drc(match.group(0)))
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match = re.search(r"(.*)_extend_(.*)", rule)
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if match:
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setattr(self, match.group(0), drc(match.group(0)))
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# Create the maximum well extend active that gets used
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# by cells to extend the wells for interaction with other cells
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from tech import layer
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self.well_extend_active = 0
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if "nwell" in layer:
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self.well_extend_active = max(self.well_extend_active, self.nwell_extend_active)
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if "pwell" in layer:
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self.well_extend_active = max(self.well_extend_active, self.pwell_extend_active)
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# The active offset is due to the well extension
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if "pwell" in layer:
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self.pwell_enclose_active = drc("pwell_enclose_active")
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else:
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self.pwell_enclose_active = 0
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if "nwell" in layer:
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self.nwell_enclose_active = drc("nwell_enclose_active")
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else:
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self.nwell_enclose_active = 0
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# Use the max of either so that the poly gates will align properly
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self.well_enclose_active = max(self.pwell_enclose_active,
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self.nwell_enclose_active,
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self.active_space)
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# These are for debugging previous manual rules
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if False:
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print("poly_width", self.poly_width)
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print("poly_space", self.poly_space)
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print("m1_width", self.m1_width)
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print("m1_space", self.m1_space)
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print("m2_width", self.m2_width)
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print("m2_space", self.m2_space)
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print("m3_width", self.m3_width)
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print("m3_space", self.m3_space)
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print("m4_width", self.m4_width)
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print("m4_space", self.m4_space)
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print("active_width", self.active_width)
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print("active_space", self.active_space)
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print("contact_width", self.contact_width)
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print("poly_to_active", self.poly_to_active)
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print("poly_extend_active", self.poly_extend_active)
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print("poly_to_contact", self.poly_to_contact)
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print("active_contact_to_gate", self.active_contact_to_gate)
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print("poly_contact_to_gate", self.poly_contact_to_gate)
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print("well_enclose_active", self.well_enclose_active)
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print("implant_enclose_active", self.implant_enclose_active)
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print("implant_space", self.implant_space)
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import sys
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sys.exit(1)
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def setup_multiport_constants(self):
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@classmethod
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def setup_multiport_constants(design):
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"""
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These are contants and lists that aid multiport design.
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Ports are always in the order RW, W, R.
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@ -231,32 +238,32 @@ class design(hierarchy_design):
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total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
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# These are the read/write port indices.
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self.readwrite_ports = []
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design.readwrite_ports = []
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# These are the read/write and write-only port indices
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self.write_ports = []
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design.write_ports = []
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# These are the write-only port indices.
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self.writeonly_ports = []
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design.writeonly_ports = []
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# These are the read/write and read-only port indices
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self.read_ports = []
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design.read_ports = []
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# These are the read-only port indices.
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self.readonly_ports = []
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design.readonly_ports = []
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# These are all the ports
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self.all_ports = list(range(total_ports))
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design.all_ports = list(range(total_ports))
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# The order is always fixed as RW, W, R
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port_number = 0
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for port in range(OPTS.num_rw_ports):
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self.readwrite_ports.append(port_number)
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self.write_ports.append(port_number)
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self.read_ports.append(port_number)
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design.readwrite_ports.append(port_number)
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design.write_ports.append(port_number)
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design.read_ports.append(port_number)
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port_number += 1
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for port in range(OPTS.num_w_ports):
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self.write_ports.append(port_number)
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self.writeonly_ports.append(port_number)
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design.write_ports.append(port_number)
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design.writeonly_ports.append(port_number)
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port_number += 1
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for port in range(OPTS.num_r_ports):
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self.read_ports.append(port_number)
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self.readonly_ports.append(port_number)
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design.read_ports.append(port_number)
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design.readonly_ports.append(port_number)
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port_number += 1
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def analytical_power(self, corner, load):
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@ -266,3 +273,7 @@ class design(hierarchy_design):
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total_module_power += inst.mod.analytical_power(corner, load)
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return total_module_power
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design.setup_drc_constants()
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design.setup_layer_constants()
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design.setup_multiport_constants()
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@ -13,7 +13,6 @@ from tech import drc, GDS
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from tech import layer as techlayer
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from tech import layer_indices
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from tech import layer_stacks
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from tech import preferred_directions
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import os
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from globals import OPTS
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from vector import vector
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@ -537,10 +536,6 @@ class layout():
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position_list=coordinates,
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widen_short_wires=widen_short_wires)
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def get_preferred_direction(self, layer):
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""" Return the preferred routing directions """
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return preferred_directions[layer]
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def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None):
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""" Add a three layer via structure. """
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from sram_factory import factory
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@ -10,7 +10,7 @@ import utils
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from tech import GDS, layer
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class bitcell(bitcell_base.bitcell_base):
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"""
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