Default bitcell opt1

compiler/characterizer/simulation.py

@@ -527,12 +527,10 @@ class simulation():
         """
         Gets the signal name associated with the bitlines in the bank.
         """
-        
         cell_mod = factory.create(module_type=OPTS.bitcell)
         cell_bl = cell_mod.get_bl_name(port)
         cell_br = cell_mod.get_br_name(port)
-        
-        # Only a single path should contain a single s_en name. Anything else is an error.
+            
         bl_names = []
         exclude_set = self.get_bl_name_search_exclusions()
         for int_net in [cell_bl, cell_br]:

compiler/custom/s8_bitcell.py

@@ -35,7 +35,7 @@ class s8_bitcell(bitcell_base.bitcell_base):
         type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
     storage_nets = ['Q', 'Q_bar']
 
-    def __init__(self, version, name=""):
+    def __init__(self, version="opt1", name=""):
         # Ignore the name argument
 
         if version == "opt1":

compiler/pgates/pinv.py

@@ -88,8 +88,8 @@ class pinv(pgate.pgate):
             self.nmos_width = self.nmos_size * drc("minwidth_tx")
             self.pmos_width = self.pmos_size * drc("minwidth_tx")
             if OPTS.tech_name == "sky130":
-                (self.nmos_width, self.tx_mults) = self.bin_width("nmos", self.nmos_width)
-                (self.pmos_width, self.tx_mults) = self.bin_width("pmos", self.pmos_width)
+                (self.nmos_width, self.tx_mults) = pgate.pgate.best_bin("nmos", self.nmos_width)
+                (self.pmos_width, self.tx_mults) = pgate.pgate.best_bin("pmos", self.pmos_width)
             return
         
         # Do a quick sanity check and bail if unlikely feasible height