mirror of https://github.com/VLSIDA/OpenRAM.git
Fix row and col cap custom names by adding default.
This commit is contained in:
parent
29ac541b28
commit
1de545fc8e
|
|
@ -146,6 +146,12 @@ class cell_properties():
|
|||
self.names["replica_bitcell"] = "replica_cell_6t"
|
||||
self.names["replica_bitcell_1rw_1r"] = "replica_cell_1rw_1r"
|
||||
self.names["replica_bitcell_1r_1w"] = "replica_cell_1r_1w"
|
||||
self.names["col_cap_bitcell_6t"] = "col_cap_cell_6t"
|
||||
self.names["col_cap_bitcell_1rw_1r"] = "col_cap_cell_1rw_1r"
|
||||
self.names["col_cap_bitcell_1r_1w"] = "col_cap_cell_1r_1w"
|
||||
self.names["row_cap_bitcell_6t"] = "row_cap_cell_6t"
|
||||
self.names["row_cap_bitcell_1rw_1r"] = "row_cap_cell_1rw_1r"
|
||||
self.names["row_cap_bitcell_1r_1w"] = "row_cap_cell_1r_1w"
|
||||
|
||||
self._bitcell = _bitcell._default()
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue