mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 and small fix
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@ -28,7 +28,7 @@ class design(hierarchy_design):
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# depending on the number of ports.
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if name in props.names:
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if isinstance(name , list):
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if type(name) is list:
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num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
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cell_name = props.names[name][num_ports]
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else:
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