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Fix original pin name bug in bitcell too.

This commit is contained in:
mrg 2020-11-19 15:12:02 -08:00
parent 033111a5f3
commit b77f168270
2 changed files with 3 additions and 2 deletions
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3
compiler/bitcells/pbitcell.py
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@ -1120,7 +1120,7 @@ class pbitcell(bitcell_base.bitcell_base):
def get_wl_name(self, port=0):
"""Get wl name by port"""
debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
debug.check(port < 2, "Two ports for bitcell_2port only.")
return "wl{}".format(port)
def get_stage_effort(self, load):
@ -1163,6 +1163,7 @@ class pbitcell(bitcell_base.bitcell_base):
return
pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
# Edges added wl->bl, wl->br for every port except write ports
rw_pin_names = zip(self.r_wl_names, self.r_bl_names, self.r_br_names)
r_pin_names = zip(self.rw_wl_names, self.rw_bl_names, self.rw_br_names)

2
compiler/bitcells/replica_bitcell_2port.py
View File

@ -41,7 +41,7 @@ class replica_bitcell_2port(bitcell_base.bitcell_base):
def build_graph(self, graph, inst_name, port_nets):
"""Adds edges to graph. Multiport bitcell timing graph is too complex
to use the add_graph_edges function."""
pin_dict = {pin: port for pin, port in zip(self.pin_names, port_nets)}
pin_dict = {pin: port for pin, port in zip(self.get_original_pin_names(), port_nets)}
# Edges hardcoded here. Essentially wl->bl/br for both ports.
# Port 0 edges
graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)