mirror of https://github.com/VLSIDA/OpenRAM.git
Remove hardcoded structure
This commit is contained in:
parent
3c2e8754e0
commit
8a9bf2d4f0
|
|
@ -56,8 +56,7 @@ class s8_bitcell(bitcell_base.bitcell_base):
|
|||
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"],
|
||||
"s8sram_cell\x00")
|
||||
layer["mem"])
|
||||
|
||||
def get_all_wl_names(self):
|
||||
""" Creates a list of all wordline pin names """
|
||||
|
|
|
|||
Loading…
Reference in New Issue