mirror of https://github.com/VLSIDA/OpenRAM.git
Use cell_name in col and row caps too.
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1890385be1
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@ -22,9 +22,11 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
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type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
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"POWER", "GROUND"]
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def __init__(self, name="col_cap_cell_1rw_1r"):
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def __init__(self, name="col_cap_cell_1rw_1r", cell_name=None):
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if not cell_name:
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cell_name = name
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# Ignore the name argument
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bitcell_base.bitcell_base.__init__(self, name)
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bitcell_base.bitcell_base.__init__(self, name, cell_name)
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debug.info(2, "Create col_cap bitcell 1rw+1r object")
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self.no_instances = True
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@ -22,9 +22,10 @@ class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
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props.bitcell.cell_1rw1r.pin.gnd]
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type_list = ["INPUT", "INPUT", "GROUND"]
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def __init__(self, name="row_cap_cell_1rw_1r"):
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# Ignore the name argument
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bitcell_base.bitcell_base.__init__(self, name)
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def __init__(self, name="row_cap_cell_1rw_1r", cell_name=None):
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if not cell_name:
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cell_name = name
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bitcell_base.bitcell_base.__init__(self, name, cell_name)
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debug.info(2, "Create row_cap bitcell 1rw+1r object")
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self.no_instances = True
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