mirror of https://github.com/VLSIDA/OpenRAM.git
Clean up custom cells
This commit is contained in:
mrg
parent
8a9bf2d4f0
commit
03e1b9c50d
|
|
@ -10,7 +10,7 @@ import utils
|
|||
from tech import GDS, layer
|
||||
from tech import cell_properties as props
|
||||
import bitcell_base
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
class s8_bitcell(bitcell_base.bitcell_base):
|
||||
"""
|
||||
|
|
@ -38,7 +38,6 @@ class s8_bitcell(bitcell_base.bitcell_base):
|
|||
def __init__(self, version, name=""):
|
||||
# Ignore the name argument
|
||||
|
||||
|
||||
if version == "opt1":
|
||||
self.name = "s8sram_cell_opt1"
|
||||
elif version == "opt1a":
|
||||
|
|
@ -49,14 +48,12 @@ class s8_bitcell(bitcell_base.bitcell_base):
|
|||
|
||||
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
|
||||
|
||||
|
||||
|
||||
self.add_pin_types(self.type_list)
|
||||
self.nets_match = self.do_nets_exist(self.storage_nets)
|
||||
self.nets_match = self.do_nets_exist(self.storage_nets)
|
||||
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
|
||||
def get_all_wl_names(self):
|
||||
""" Creates a list of all wordline pin names """
|
||||
|
|
|
|||
|
|
@ -9,16 +9,13 @@
|
|||
import debug
|
||||
import design
|
||||
import utils
|
||||
from globals import OPTS
|
||||
from tech import parameter, drc, layer, GDS
|
||||
from tech import layer, GDS
|
||||
|
||||
|
||||
class s8_col_end(design.design):
|
||||
|
||||
|
||||
def __init__(self, version, name=""):
|
||||
super().__init__(name)
|
||||
pin_names = []
|
||||
type_list = []
|
||||
|
||||
if version == "colend":
|
||||
self.name = "s8sram16x16_colend"
|
||||
|
|
@ -32,10 +29,9 @@ class s8_col_end(design.design):
|
|||
debug.error("Invalid type for col_end", -1)
|
||||
design.design.__init__(self, name=self.name)
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"],
|
||||
structure)
|
||||
pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
# pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -9,16 +9,13 @@
|
|||
import debug
|
||||
import design
|
||||
import utils
|
||||
from globals import OPTS
|
||||
from tech import parameter, drc, layer, GDS
|
||||
from tech import layer, GDS
|
||||
|
||||
|
||||
class s8_corner(design.design):
|
||||
|
||||
|
||||
def __init__(self, location, name=""):
|
||||
super().__init__(name)
|
||||
pin_names = []
|
||||
type_list = []
|
||||
|
||||
if location == "ul":
|
||||
self.name = "s8sram16x16_corner"
|
||||
|
|
@ -32,6 +29,6 @@ class s8_corner(design.design):
|
|||
debug.error("Invalid s8_corner location", -1)
|
||||
design.design.__init__(self, name=self.name)
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
# pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
|
|
|
|||
|
|
@ -9,16 +9,13 @@
|
|||
import debug
|
||||
import design
|
||||
import utils
|
||||
from globals import OPTS
|
||||
from tech import parameter, drc, layer, GDS
|
||||
from tech import layer, GDS
|
||||
|
||||
|
||||
class s8_internal(design.design):
|
||||
|
||||
|
||||
def __init__(self, version, name=""):
|
||||
super().__init__(name)
|
||||
pin_names = []
|
||||
type_list = []
|
||||
|
||||
if version == "wlstrap":
|
||||
self.name = "s8sram_wlstrap"
|
||||
|
|
@ -30,6 +27,6 @@ class s8_internal(design.design):
|
|||
debug.error("Invalid version", -1)
|
||||
design.design.__init__(self, name=self.name)
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
# pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
|
|
|
|||
|
|
@ -8,11 +8,11 @@
|
|||
import design
|
||||
import debug
|
||||
import utils
|
||||
from tech import GDS,layer,drc,parameter,cell_properties
|
||||
from tech import GDS, layer, drc, parameter, cell_properties
|
||||
from tech import cell_properties as props
|
||||
|
||||
from globals import OPTS
|
||||
|
||||
|
||||
class replica_bitcell(design.design):
|
||||
"""
|
||||
A single bit cell (6T, 8T, etc.)
|
||||
|
|
@ -22,7 +22,7 @@ class replica_bitcell(design.design):
|
|||
|
||||
if props.compare_ports(props.bitcell.split_wl):
|
||||
pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
|
||||
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
|
||||
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT" , "POWER", "GROUND"]
|
||||
else:
|
||||
pin_names = [props.bitcell.cell_6t.pin.bl,
|
||||
props.bitcell.cell_6t.pin.br,
|
||||
|
|
@ -30,18 +30,8 @@ class replica_bitcell(design.design):
|
|||
props.bitcell.cell_6t.pin.vdd,
|
||||
props.bitcell.cell_6t.pin.gnd]
|
||||
|
||||
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
|
||||
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
|
||||
|
||||
if not OPTS.netlist_only:
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"],
|
||||
"s8sram_cell\x00")
|
||||
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
|
||||
else:
|
||||
(width,height) = (0,0)
|
||||
pin_map = []
|
||||
|
||||
def __init__(self, version, name=""):
|
||||
# Ignore the name argument
|
||||
|
||||
|
|
@ -56,11 +46,14 @@ class replica_bitcell(design.design):
|
|||
design.design.__init__(self, "replica_cell_6t")
|
||||
debug.info(2, "Create replica bitcell object")
|
||||
|
||||
self.width = replica_bitcell.width
|
||||
self.height = replica_bitcell.height
|
||||
self.pin_map = replica_bitcell.pin_map
|
||||
self.pin_map = utils.get_libcell_pins(self.pin_names, self.name, GDS["unit"])
|
||||
|
||||
self.add_pin_types(self.type_list)
|
||||
|
||||
(self.width, self.height) = utils.get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
|
||||
def get_stage_effort(self, load):
|
||||
parasitic_delay = 1
|
||||
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
|
||||
|
|
|
|||
Loading…
Reference in New Issue