Merge multiple cell_name fix.

compiler/base/design.py

@@ -28,11 +28,11 @@ class design(hierarchy_design):
         # depending on the number of ports.
 
         if name in props.names:
-            if type(name) is list:
-                num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports
+            if type(props.names[name]) is list:
+                num_ports = OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports - 1
                 cell_name = props.names[name][num_ports]
             else:
-                cell_name = props.name[name]
+                cell_name = props.names[name]
 
         elif not cell_name:
             cell_name = name

compiler/base/hierarchy_design.py

@@ -21,22 +21,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
     name_map = []
 
     def __init__(self, name, cell_name):
-        self.gds_file = OPTS.openram_tech + "gds_lib/" + cell_name + ".gds"
-        self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp"
-
-        # If we have a separate lvs directory, then all the lvs files
-        # should be in there (all or nothing!)
-        try:
-            lvs_subdir = tech.lvs_lib
-        except AttributeError:
-            lvs_subdir = "lvs_lib"
-        lvs_dir = OPTS.openram_tech + lvs_subdir + "/"
-
-        if os.path.exists(lvs_dir):
-            self.lvs_file = lvs_dir + cell_name + ".sp"
-        else:
-            self.lvs_file = self.sp_file
-
         self.drc_errors = "skipped"
         self.lvs_errors = "skipped"
 

compiler/base/hierarchy_layout.py

@@ -36,6 +36,8 @@ class layout():
         self.name = name
         self.cell_name = cell_name
         
+        self.gds_file = OPTS.openram_tech + "gds_lib/" + cell_name + ".gds"
+        
         self.width = None
         self.height = None
         self.bounding_box = None

compiler/base/hierarchy_spice.py

@@ -10,6 +10,7 @@ import re
 import os
 import math
 import tech
+from globals import OPTS
 from pprint import pformat
 from delay_data import delay_data
 from wire_spice_model import wire_spice_model
@@ -32,6 +33,21 @@ class spice():
         self.name = name
         self.cell_name = cell_name
 
+        self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp"
+
+        # If we have a separate lvs directory, then all the lvs files
+        # should be in there (all or nothing!)
+        try:
+            lvs_subdir = tech.lvs_lib
+        except AttributeError:
+            lvs_subdir = "lvs_lib"
+        lvs_dir = OPTS.openram_tech + lvs_subdir + "/"
+
+        if os.path.exists(lvs_dir):
+            self.lvs_file = lvs_dir + cell_name + ".sp"
+        else:
+            self.lvs_file = self.sp_file
+        
         self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
         # Holds subckts/mods for this module
         self.mods = []