mirror of https://github.com/VLSIDA/OpenRAM.git
Remove another boundary subcell
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parent
8d5db50062
commit
3648401e67
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@ -9,16 +9,14 @@
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import debug
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import design
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import utils
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from globals import OPTS
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from tech import parameter, drc, layer, GDS
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from tech import layer, GDS
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class s8_row_end(design.design):
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def __init__(self, version, name=""):
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super().__init__(name)
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pin_names = ["wl", "vpwr"]
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type_list = ["OUTPUT", "POWER"]
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if version == "rowend":
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self.name = "s8sram16x16_rowend"
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@ -28,11 +26,9 @@ class s8_row_end(design.design):
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debug.error("Invalid type for row_end", -1)
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design.design.__init__(self, name=self.name)
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(self.width, self.height) = utils.get_libcell_size(self.name,
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GDS["unit"],
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layer["mem"],
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"s8sram16x16_rowend_ce\x00")
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GDS["unit"],
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layer["mem"])
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self.pin_map = utils.get_libcell_pins(pin_names, self.name, GDS["unit"])
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self.add_pin("wl", "OUTPUT")
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self.add_pin("vpwr", "POWER")
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