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OpenRAM
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3943 Commits

Author SHA1 Message Date
Bugra Onal ed0c93ba55 Only add drc errors from compiler 2023-07-10 14:05:44 -07:00
Bugra Onal eddc9af45b Merge branch 'dev' into char 2023-07-10 13:55:50 -07:00
Sam Crow 4e649aad6b fix typo bug in spice comments code 2023-07-10 13:21:24 -07:00
Bugra Onal 0ad619f04c Added bl, sen and cell format options 2023-07-10 12:32:58 -07:00
Eren Dogan 6b0b4c2def Create fake pins on the ring and route others to them 2023-07-10 09:24:16 -07:00
Eren Dogan 4a61874888 Add supply ring pins around the layout area 2023-07-09 18:53:21 -07:00
Bugra Onal 7220e0a483 sim_exe will be found everytime with func and char 2023-07-07 12:39:19 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 468c972acb add optional guard band to delay chain sizing 2023-07-05 16:34:42 -07:00
Sam Crow d65ccfcc95 fix column mux without rbl start_bit to 0 2023-07-05 13:17:46 -07:00
Sam Crow b4a9784835 model vth delay swing delay 2023-07-05 12:17:48 -07:00
Sam Crow 5235cf9667 model p_en and wl_en delays in delay chain sizing 2023-07-03 17:02:11 -07:00
Eren Dogan bb35ac2f90 Include new wires while routing the pins 2023-07-03 14:04:26 -07:00
Eren Dogan 0938e7ec9a Fix probes not being blocked correctly 2023-07-03 13:34:27 -07:00
Eren Dogan 78be525ea0 Use minimum spanning tree to route same type of pins together 2023-07-01 16:14:56 -07:00
Sam Crow e1865083d7 incomplete work on improved delay modeling 2023-06-29 14:44:42 -07:00
Eren Dogan 5bf629f3e5 Prevent DRC violations for vdd and gnd pins 2023-06-28 20:55:49 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
Sam Crow 28ea93bd0a convert 1-indexing to 0-indexing 2023-06-25 11:03:10 -07:00
Sam Crow 006eacd6d0 add pinout message output 2023-06-25 10:46:58 -07:00
Sam Crow 8992c0fb68 first approximation of delay values 2023-06-20 16:22:03 -07:00
Eren Dogan a47bc7ebee Prevent multiple dog-legs in non-preferred direction 2023-06-15 11:08:13 -07:00
Sam Crow dbc9de6c9a implement relationship between delay pinouts 2023-06-14 17:10:07 -07:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia b9e61f346a Merge branch 'dev' into openROM-verilogoutput 
To test recent changes with ROM verilog output
 2023-06-14 12:26:07 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Sam Crow bf516a927d add skeleton for delay chain sizing 2023-06-13 13:44:32 -07:00
Sam Crow fee90283b9 add spacing and a comment 2023-06-12 16:56:44 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Sam Crow 96a1d400fa add single port bank test for norbl 2023-06-12 12:50:50 -07:00
Sam Crow 266bcd9cf2 consolidate failing xyce delay tests to one in skip list 2023-06-11 14:52:26 -07:00
Sam Crow 854bff9dce add norbl bank tests to sky130 skipped tests 2023-06-08 13:22:12 -07:00
Sam Crow 7048a072e2 add local/global array sky130 skipped tests 2023-06-08 13:16:27 -07:00
Sam Crow 44ed72b50d add has_rbl=True arg to tests 2023-06-08 13:10:03 -07:00
Sam Crow ce622952ef route rbl conditionally 2023-06-08 12:36:31 -07:00
Sam Crow a51b71d460 update copyright 2023-06-08 12:36:12 -07:00
Sam Crow 973b5512f0 add new failing sky130 tests to skip list 2023-06-07 17:29:58 -07:00
Sam Crow dcf95460d0 sort sky130 skipped tests numerically 2023-06-07 16:09:18 -07:00
Sam Crow 9256ae8c00 fix typos and standardize multiport control logic tests 2023-06-07 16:04:54 -07:00
samuelkcrow afd3b782b9 remove cs_bar signal bus from all control logics 2023-06-07 15:53:15 -07:00
samuelkcrow a48842ff72 fix code format issues from 00 test 2023-06-07 15:52:25 -07:00
samuelkcrow b9492051b6 use control_logic_base in control_logic_delay 2023-06-07 15:51:19 -07:00
Sam Crow a70dcc5c85 reword comments in replica bitcell array module 2023-06-06 14:43:18 -07:00
Sam Crow 9fdf8a8341 ommit rbl pins in sram_1bank when appropriate 2023-06-06 13:15:17 -07:00
Sam Crow 157935c915 update test/module imports related to delay control 2023-06-06 13:12:20 -07:00
Eren Dogan 15b4e4dbe8 Fix DRC spacing in Hanan router 2023-06-05 19:33:45 -07:00
Sam Crow 5fef78dbfa Merge branch 'no_rbl' into delay_ctrl 2023-06-05 16:31:07 -07:00
Sam Crow 2f5d3b6faf Merge branch 'dev' into delay_ctrl 2023-06-05 16:24:48 -07:00
Sam Crow df827fbd3d add norbl whole sram test 2023-06-05 15:26:26 -07:00
Sam Crow 5b10f06be6 place wl_en pin on wl drivers in absence of rbl_wl driver 2023-06-05 15:26:11 -07:00
Sam Crow 0b5039cc89 make norbl bank test executable 2023-06-05 12:08:22 -07:00
Eren Dogan 48a148003a Include other pins as blockages in Hanan router 2023-06-05 11:27:05 -07:00
Sam Crow 23232fd376 Merge branch 'dev' into no_rbl 2023-06-05 11:03:22 -07:00
Eren Dogan 8f1af0ebb7 Reduce the number of shapes on Hanan paths 2023-06-04 10:56:50 -07:00
Eren Dogan 021da25cd6 Include all blockages inside the routing region 2023-06-04 08:46:59 -07:00
Eren Dogan 4fe5aa49e4 Reorganize utility functions for Hanan router 2023-06-01 14:24:40 -07:00
Eren Dogan e3d8ad13b2 Remove blocked Hanan node connections 2023-05-30 20:09:10 -07:00
Eren Dogan 2799c106bd Divide long code into sub-functions 2023-05-30 13:36:38 -07:00
Eren Dogan 136d4564a2 Use less memory when removing blocked Hanan points 2023-05-30 11:10:34 -07:00
Eren Dogan 9f75e68a92 Simplify Hanan graph generation 2023-05-29 21:49:00 -07:00
Eren Dogan 6079152092 Cleanup Hanan router 2023-05-29 12:43:43 -07:00
Eren Dogan e1e24f6d06 Rename gridless router 2023-05-29 09:18:55 -07:00
Eren Dogan 533c1c9472 Fix gridless router for tall and fat pins 2023-05-28 21:25:11 -07:00
Bugra Onal 054b7cd47d Fixed code format 2023-05-23 13:47:02 -07:00
Bugra Onal f16a40af02 Renamed char and func unit tests 2023-05-23 13:46:05 -07:00
Bugra Onal 15c5e57d77 functional should use full sp file path 2023-05-23 10:58:43 -07:00
Bugra Onal e13cc76ac3 Fix Python 3.11 random change 2023-05-23 10:58:17 -07:00
Bugra Onal 6841de4a50 reflect the changes to sram.py from dev 2023-05-23 10:36:49 -07:00
Eren Dogan 33f1b924a4 Avoid blockages when connecting Hanan points 2023-05-22 18:16:49 -07:00
Eren Dogan 648a631a28 Use Hanan points to generate the routing graph 2023-05-22 13:08:21 -07:00
Bugra Onal 217b0981a2 Use subprocess.run instead of subprocess.call 2023-05-16 15:07:31 -07:00
Bugra Onal b9123571f4 Fix functional script spice file name and unit test 2023-05-16 15:06:49 -07:00
Sam Crow 2709f61317 fix index out of bounds bug 2023-05-16 14:38:51 -07:00
Sam Crow 79e5c1ad86 add dp norbl bank test 2023-05-16 14:36:58 -07:00
Bugra Onal dbb8bb85cb Fixed golden values for ngspice delay tests 2023-05-15 16:28:35 -07:00
Eren Dogan 8ac95c19a4 Add optional $CONDA_HOME environment variable 2023-05-11 16:42:29 -07:00
Eren Dogan cd339ebbd0 Add A* algorithm for navigation router 2023-05-09 13:23:01 -07:00
Eren Dogan 909ac6ce68 Add initial files for navigation router 2023-05-04 20:51:30 -07:00
Eren Dogan f2235c2457 Cleanup globals.py 2023-05-04 20:47:53 -07:00
Eren Dogan 420ce01b46 Throw error if can't make temp directory 2023-05-04 20:27:59 -07:00
Sam Crow f5bc031d83 Merge branch 'dev' into no_rbl 2023-05-03 15:24:03 -07:00
Sam Crow db8ab303c7 Merge branch 'dev' into sky130_custom_modules 2023-05-03 14:12:52 -07:00
Sam Crow 0e781dd224 cast valid addresses to list for python 3.11 requirement 2023-05-01 17:05:07 -07:00
Eren Dogan 938da3b369 Merge branch 'sky130_regress' into dev 2023-04-26 12:33:21 -07:00
Sam Crow 123149503b add a bank test with no rbl 2023-04-25 09:27:56 -07:00
Sam Crow 744ba0e892 fix precharge bit offsets in no rbl case 2023-04-25 09:24:18 -07:00
Bugra Onal afe37e5915 sp file sram instance name fix 2023-04-19 18:57:38 -07:00
Bugra Onal b2b7e1fa4d fixed the test name 2023-04-19 18:51:34 -07:00
Bugra Onal 3f94e22860 Fixed memchar test output name 2023-04-19 18:44:09 -07:00
Bugra Onal 07411892c1 Moved memchar test tmp dir to results 2023-04-19 18:33:43 -07:00
Bugra Onal 44ca70bd16 Updated golden values for freepdk 2023-04-19 17:23:46 -07:00
Bugra Onal bd7b2c22c7 Added spice files for the command line char 2023-04-19 17:23:00 -07:00
Bugra Onal 6af9c556a9 Fix char tests 2023-04-19 12:41:39 -07:00
Eren Dogan 51ddb08385 Enable sky130 regression but disable failing tests 2023-04-13 22:12:46 -07:00
Bugra Onal 773ea1af0d include statement position fixed 2023-04-12 15:45:19 -07:00
Eren Dogan ed8242daf8 Add OPENRAM_TECH to package namespace 2023-04-12 13:18:00 -07:00
Bugra Onal dae275c508 Merge branch 'dev' into char 2023-04-12 12:00:31 -07:00
Bugra Onal 8d0c46d069 Fix import issue 2023-04-12 11:48:20 -07:00
Sam Crow eea748ff3e remove test for unsupported config 2023-04-10 11:16:10 -07:00
Sam Crow 670b40642b add no rbl tests to 15 global array tests 2023-04-10 10:38:52 -07:00
Eren Dogan 095e0baddd Remove CHECKPOINT_OPTS since it is not used 2023-04-07 12:32:29 -07:00
Sam Crow dff94a032e fix bug in right rbl dual port replica array test 2023-04-07 11:30:15 -07:00
Sam Crow 5b701d828e remove unused function 2023-04-07 10:32:11 -07:00
Sam Crow 3c7f35d295 add no rbl support to bank module 2023-04-07 10:02:38 -07:00
Sam Crow efbb658784 add no rbl support to port address 2023-04-05 16:04:20 -07:00
Sam Crow ae6d271602 add support for no rbl to port data 2023-04-05 15:33:45 -07:00
Sam Crow d00ba73bc9 add no rbl support to global array 2023-04-05 14:47:15 -07:00
Sage Walker b2bcbddd01 ROM binary file support 2023-04-03 16:04:12 -07:00
Sam Crow 83b25138d0 apply 14* standard to 15_local tests 2023-04-03 10:11:49 -07:00
Sam Crow 9181f6a218 standardize 14* test structure 2023-04-03 10:08:57 -07:00
Jacob Walker 0b056dca54 fixed rom bank test name 2023-03-30 18:44:55 -07:00
Jacob Walker 52791a2719 a space 2023-03-30 11:30:50 -07:00
Jacob Walker c1fb3cab6c 1kb rom DRC clean 2023-03-30 11:30:50 -07:00
Jacob Walker 7805fcb21e more top level routing cleanup 2023-03-30 11:30:50 -07:00
Jacob Walker fef9902c45 rom base passing tests with top level routing 2023-03-30 11:30:50 -07:00
mrg 7c453e80be Simplify ROM test. 2023-03-30 11:30:50 -07:00
mrg af0a6d32fb Remove old skip tests 2023-03-30 11:30:50 -07:00
mrg 2075d244cb Change ROM test permissions to include x 2023-03-30 11:30:50 -07:00
Jacob Walker 4c34a54d32 top level boundary fixes 2023-03-30 11:30:50 -07:00
Jacob Walker 7fe5ed5c41 edge routing 2023-03-30 11:30:50 -07:00
Jacob Walker 09f9c4cc20 some rom bank cleanup 2023-03-30 11:30:50 -07:00
mrg 56e14113aa Change rom_base_bank name and top pin names 2023-03-30 11:30:50 -07:00
mrg d2b5be0130 Add exclude tests for ROMs 2023-03-30 11:30:50 -07:00
mrg fe65a20431 Rename ROM unit tests. 2023-03-30 11:30:50 -07:00
Jacob Walker eec0f02bb8 skip test file 2023-03-30 11:30:50 -07:00
Jacob Walker b50ec272da updated top level rom unit tests 2023-03-30 11:30:50 -07:00
Jacob Walker 41f0b9a412 rom compiler top level 2023-03-30 11:30:50 -07:00
Jacob Walker 2d5199961d revert changes to pinvbuf 2023-03-30 11:30:50 -07:00
Jacob Walker 382c91f342 precharge array test passing sky130 2023-03-30 11:30:50 -07:00
Jacob Walker 92251fe61e more code cleaning 2023-03-30 11:30:50 -07:00
Jacob Walker 90cf382a43 removed hardcoded DRC rule 2023-03-30 11:30:50 -07:00
Jacob Walker 0cb4459b4b changed ROM test data path 2023-03-30 11:30:50 -07:00
Jacob Walker af0209ec96 passing code style 2023-03-30 11:30:50 -07:00
Jacob Walker 79efff9ca6 code cleanup and updated copyright 2023-03-30 11:30:50 -07:00
Jacob Walker bbf2cd2913 Changes for test generation and simulation 2023-03-30 11:30:50 -07:00
Jacob Walker 89c7d50bd1 added row of nmos to end of array for precharge 2023-03-30 11:30:50 -07:00
SWalker f847721500 changes to control logic, invert polarity of precharge 2023-03-30 11:30:50 -07:00
SWalker 9cefe5da7c added unrouted output buffers 2023-03-30 11:30:50 -07:00
SWalker 764601a721 added binning to precharge pmos 2023-03-30 11:30:50 -07:00
Jesse Cirimelli-Low 6981cfa58b add example of writing out simulation netlist 2023-03-30 11:30:50 -07:00
Jacob Walker 736bd51fe1 add top level pins for sim 2023-03-30 11:30:50 -07:00
Jacob Walker 81bf2d7ae7 fixed decode lvs 2023-03-30 11:30:50 -07:00
Jacob Walker 16df8e0e43 fixing decoder lvs 2023-03-30 11:30:50 -07:00
Jacob Walker 559300e5cc taps in main array and decoder 2023-03-30 11:30:50 -07:00
Jacob Walker f7aed247fd column control and address precharge 2023-03-30 11:30:50 -07:00
Jacob Walker ce8197d206 pitch match decoder and array 2023-03-30 11:30:50 -07:00
Jacob Walker e697efa5f6 fixed base array lvs 2023-03-30 11:30:50 -07:00
Jacob Walker b2631b60ff updated imports to match upstream dev openram 2023-03-30 11:30:50 -07:00
Jacob Walker 63925bd48e Decoder array and start of rom bank 2023-03-30 11:30:50 -07:00
Jacob Walker bc8d564dbf array with poly straps passing drc/lvs 2023-03-30 11:30:50 -07:00
Jacob Walker aea3c0ad01 passing drc/lvs on 4x4 rom array 2023-03-30 11:30:50 -07:00
Jacob Walker a3e271f6fb reoriented cell and added tap cell 2023-03-30 11:30:50 -07:00
Jacob Walker 7309af7e29 base and dummy array alignment in sky130 2023-03-30 11:30:50 -07:00
Jacob Walker d7ac26a053 array generation and bitline routing with array module 2023-03-30 11:30:50 -07:00
Jacob Walker 4db5c3be26 basic nmos array, for nand rom 2023-03-30 11:30:50 -07:00
Sam Crow 299512eba2 standardize array tests 2023-03-22 18:56:52 -07:00
Eren Dogan 6eebef8c72 Fix typo in Makefile 2023-03-16 14:40:24 -07:00
mrg 8ea100b52e Split pbitcell tests to fix factory.reset() bug. 2023-03-14 08:50:00 -07:00
Eren Dogan 16490e9928 Merge branch 'conda' into dev 2023-03-13 16:10:35 -07:00
Eren Dogan 650b6e513c Remove the hack used for unit tests running on docker 2023-03-10 16:35:22 -08:00
mrg c9bf3c1261 Remove factory.reset from all unit tests as we no longer use regress.py. 2023-03-10 10:44:54 -08:00
Sam Crow e20f28580f support no rbls in local array 2023-03-09 14:44:05 -08:00
Sam Crow 710f0fbae5 update local/global tests for no rbls 2023-03-09 14:37:07 -08:00
Sam Crow 41344a980b change array modules to allow rbl=[0, 0] 2023-03-09 10:23:28 -08:00
Sam Crow 7abaf0463e create no rbl no dummy tests 2023-03-09 10:05:17 -08:00
mrg 5c173551ec Remove regress.py and skip_tests for Makefile option instead. 2023-03-02 12:44:52 -08:00
mrg 1f3bdd598a Add scn4m_subm global array test to skip test until issue is fixed. 2023-03-01 14:23:31 -08:00
mrg 49dbbb33bc Add skip tests until inverters added to sense amps. 2023-03-01 14:15:07 -08:00
mrg 58f1b55e08 Over-ride build_graph in row/col caps to remove incorrect graph error. 2023-03-01 09:25:56 -08:00
Bugra Onal 249d1b9c1d Moved sram_op and bit_polarity 2023-02-24 16:42:39 -08:00
Bugra Onal 613146520e Merge branch 'library' into char 2023-02-23 15:11:39 -08:00
Bugra Onal f7f61fee27 Format fixes 2023-02-22 12:38:47 -08:00
Bugra Onal 6eb0ecd82b fixed copyright again 2023-02-21 14:07:08 -08:00
samuelkcrow e90964fbda update copyright 2023-02-21 14:04:31 -08:00
Bugra Onal 8650315179 Updated copyright headers 2023-02-21 13:52:21 -08:00
Bugra Onal bce71af0ad Moved main scripts to root dir 2023-02-21 13:51:13 -08:00
Bugra Onal 6bdcdb8f37 Merge branch 'dev' into char 2023-02-21 13:00:47 -08:00
samuelkcrow ad4b4f66dc use capped array to create banks 2023-02-21 09:58:46 -08:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
samuelkcrow 52dcd81a08 use left_rbl instead of rbl to calculate replica column mirroring (column offset) 2023-02-20 17:28:24 -08:00
Eren Dogan b37711e643 Merge branch 'dev' into deploy_pip 2023-02-20 14:08:20 -08:00
Bugra Onal 3b69cafde7 Update Xyce char tests 2023-02-17 19:15:14 -08:00
mrg c07268d297 Disable power routing on some freepdk45 tests for issue 36 2023-02-17 17:00:04 -08:00
Eren Dogan d8a169e79f Reenable tests 2023-02-17 14:56:52 -08:00
Bugra Onal 4436c61a39 discard if precharge delay is captured 2023-02-17 14:35:09 -08:00
Bugra Onal c8a06a1317 Properly trim wrapped instances 2023-02-17 14:27:15 -08:00
Eren Dogan d3da632dc1 Fix typo in model delay test 2023-02-17 13:34:02 -08:00
Eren Dogan a7582c05dc Disable failing tests 2023-02-17 10:42:31 -08:00
Bugra Onal 7a62ec0030 Fixed typo 2023-02-16 19:36:14 -08:00
Bugra Onal 9002a8ac70 Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
Bugra Onal 4ec2dd2d1f Format fixes 2023-02-14 12:44:57 -08:00
Bugra Onal b70f919a2b Characterize only nom corner 2023-02-14 12:01:14 -08:00
samuelkcrow 51a7161cd7 fix mirroring of cap cells in cap rows 2023-02-14 10:59:00 -08:00
samuelkcrow 2565305158 fix positional getters 2023-02-13 18:45:21 -08:00
samuelkcrow 8d6d8f2f8c revert variable names to those inherited from bitcell base array 2023-02-13 18:45:21 -08:00
Eren Dogan 78e84ee8df Add version file 2023-02-07 10:30:48 -08:00
samuelkcrow 2948b08e66 copy rbl default values logic from lower array modules 2023-02-06 20:04:54 -08:00
samuelkcrow 796b1913cf fix typo in wordline var 2023-02-06 20:01:49 -08:00
samuelkcrow c256a5eb44 fix coppied functions from replica array to work correctly in capped array 2023-02-06 19:57:42 -08:00
samuelkcrow 4a22c5c56f add instance offset to capped array offset getters 2023-02-06 19:40:37 -08:00