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OpenRAM
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updated top level rom unit tests

This commit is contained in:
Jacob Walker 2023-03-09 14:12:14 -08:00
parent cd2314f008
commit b50ec272da
6 changed files with 21 additions and 80 deletions
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4
compiler/modules/rom_base_bank.py
View File

@ -55,6 +55,10 @@ class rom_base_bank(design):
self.route_stack = self.m2_stack
self.route_layer = self.route_stack[0]
if OPTS.is_unit_test:
self.create_netlist()
self.create_layout()
def create_netlist(self):
start_time = datetime.datetime.now()

1
compiler/rom.py
View File

@ -25,6 +25,7 @@ class rom():
word_size=OPTS.word_size,
words_per_row=OPTS.words_per_row,
rom_endian=OPTS.rom_endian,
scramble_bits=OPTS.scramble_bits
strap_spacing=OPTS.strap_spacing)
if name is None:

10
compiler/tests/05_rom_base_bank_1kB_test.py
View File

@ -22,9 +22,15 @@ class rom_bank_test(openram_test):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing 1kB rom cell")
test_data = "{0}/{1}/rom_data_1kB".format(os.getenv("OPENRAM_HOME"), OPTS.rom_data_dir)
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file = test_data, word_size = 1)
from openram import rom_config
conf = rom_config(strap_spacing = 8,
rom_data = test_data,
word_size = 1)
a = factory.create(module_type="rom_base_bank", rom_config=conf)
a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
self.local_check(a)

38
compiler/tests/05_rom_base_bank_2kB_test.py
View File

@ -1,38 +0,0 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import unittest
from testutils import *
import sys, os
import openram
from openram import OPTS
from openram.sram_factory import factory
from openram import debug
class rom_bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing 2kB rom cell")
test_data = "{0}/{1}/rom_data_2kB".format(os.getenv("OPENRAM_HOME"), OPTS.rom_data_dir)
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file = test_data, word_size = 1)
a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())

9
compiler/tests/05_rom_base_bank_4kB_test.py
View File

@ -24,7 +24,14 @@ class rom_bank_test(openram_test):
debug.info(1, "Testing 4kB rom cell")
test_data = "{0}/{1}/rom_data_4kB".format(os.getenv("OPENRAM_HOME"), OPTS.rom_data_dir)
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file = test_data, word_size = 2)
from openram import rom_config
conf = rom_config(strap_spacing = 8,
rom_data = test_data,
word_size = 2)
a = factory.create(module_type="rom_base_bank", rom_config=conf)
a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
self.local_check(a)

39
compiler/tests/05_rom_base_bank_8kB_test.py
View File

@ -1,39 +0,0 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import unittest
from testutils import *
import sys, os
import openram
from openram import OPTS
from openram.sram_factory import factory
from openram import debug
class rom_bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
debug.info(1, "Testing 8kB rom cell")
test_data = "{0}/{1}/rom_data_8kB".format(os.getenv("OPENRAM_HOME"), OPTS.rom_data_dir)
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file = test_data, word_size = 2)
a.sp_write(OPTS.openram_temp + 'simulation_file_8kB.sp')
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())