luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix code format issues from 00 test

This commit is contained in:
samuelkcrow 2022-08-01 15:41:09 -07:00 committed by Sam Crow
parent b9492051b6
commit a48842ff72
2 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
compiler/modules/control_logic_delay.py
View File

@ -71,7 +71,7 @@ class control_logic_delay(control_logic_base):
# wl_en_unbuf is the weak timing signal that feeds wl_en_driver
self.wl_en_and = factory.create(module_type="pand2",
size=1,
size=1,
height=dff_height)
# w_en drives every write driver
@ -207,10 +207,10 @@ class control_logic_delay(control_logic_base):
# instead I have this which duplicates the out_pin naming logic from multi_delay_chain.py
out_pins = ["out{}".format(str(pin)) for pin in self.delay_chain.pinout_list]
delay_map = zip(["in", out_pins[0], out_pins[1], out_pins[2], out_pins[3], out_pins[4]], \
["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
self.connect_vertical_bus(delay_map,
self.delay_inst,
["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
self.connect_vertical_bus(delay_map,
self.delay_inst,
self.input_bus,
self.m2_stack[::-1])
@ -244,7 +244,7 @@ class control_logic_delay(control_logic_base):
x_offset = self.place_util(self.glitch3_nand_inst, x_offset, row)
self.row_end_inst.append(self.glitch3_nand_inst)
def route_glitches(self):
glitch2_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay4", "glitch2"])

6
compiler/modules/multi_delay_chain.py
View File

@ -34,7 +34,7 @@ class multi_delay_chain(design):
# number of inverters including any fanout loads.
self.fanout_list = fanout_list
self.rows = len(self.fanout_list)
# defaults to signle output at end of delay chain
if not pinout_list:
self.pinout_list = [self.rows] # TODO: check for off-by-one here
@ -43,9 +43,9 @@ class multi_delay_chain(design):
# TODO: would like to sort and check pinout list for valid format but don't have time now
# Check pinout bounds
# debug.check(self.pinout_list[-1] <= self.rows,
# debug.check(self.pinout_list[-1] <= self.rows,
# "Ouput pin cannot exceed delay chain length.")
# debug.check(self.pinout_list[0] > 0,
# debug.check(self.pinout_list[0] > 0,
# "Delay chain output pin numbers must be positive")
self.create_netlist()