fixed decode lvs

compiler/modules/rom_base_array.py

@@ -120,7 +120,7 @@ class rom_base_array(bitcell_base_array):
             self.add_pin(bl_name, "OUTPUT")
         for wl_name in self.get_wordline_names():
             self.add_pin(wl_name, "INPUT")
-        self.add_pin("precharge_gate", "INPUT")
+        self.add_pin("precharge", "INPUT")
         self.add_pin("vdd", "POWER")
         self.add_pin("gnd", "GROUND")
 
@@ -207,7 +207,7 @@ class rom_base_array(bitcell_base_array):
         #     if self.int_bl_list[bl] == prechrg_pins[bl]:
         #         prechrg_pins[bl] = "gnd"
         
-        prechrg_pins.append("precharge_gate")
+        prechrg_pins.append("precharge")
         prechrg_pins.append("vdd")
         self.precharge_inst = self.add_inst(name="decode_array_precharge", mod=self.precharge_array)
         self.connect_inst(prechrg_pins)

compiler/modules/rom_decoder.py

@@ -245,8 +245,7 @@ class rom_decoder(design):
             # self.add_segment_center(self.inv_route_layer, addr_bar_middle + vector(0, self.inv_route_width * 0.5), addr_bar_out_pin.center() + vector(0, self.inv_route_width * 0.5), self.inv_route_width)
 
     def route_supplies(self):
-        minwidth =  drc["minwidth_{}".format(self.inv_route_layer)]
-        pitch = drc["{0}_to_{0}".format(self.inv_route_layer)]
+
         self.copy_layout_pin(self.array_inst, "vdd")
         self.copy_layout_pin(self.wordline_buf_inst, "vdd")
         self.copy_layout_pin(self.buf_inst, "vdd")
@@ -255,9 +254,8 @@ class rom_decoder(design):
         self.copy_layout_pin(self.wordline_buf_inst, "gnd")
         self.copy_layout_pin(self.buf_inst, "gnd")
 
-
         # Extend nwells to connect with eachother
-        self.extend_wells()
+        # self.extend_wells()
         
 
     def extend_wells(self):
@@ -272,11 +270,10 @@ class rom_decoder(design):
         self.add_label(text="well_left", layer="nwell", offset=offset)
         vdd_pins=self.buf_inst.get_pins("vdd").copy()
         print(vdd_pins)
-        well_by = vdd_pins[1].cy()
-        well_ll = vector(precharge_well_lx, well_by)
-
-        self.add_rect(layer="nwell", offset=well_ll, height = self.array_inst.by() - well_by, width=precharge_well_rx - precharge_well_lx)
-
+        well_by = vdd_pins[0].cy()
+        # well_ll = vector(precharge_well_lx, well_by)
+        well_ll = vector(self.buf_inst.rx(), well_by)
+        # self.add_rect(layer="nwell", offset=well_ll, height = self.array_inst.by() - well_by, width=precharge_well_rx - self.buf_inst.rx())
 
  
 

compiler/modules/rom_precharge_array.py

@@ -90,8 +90,9 @@ class rom_precharge_array(design):
     def add_pins(self):
         for col in range(self.cols):
             self.add_pin("pre_bl{0}_out".format(col), "OUTPUT")
-        self.add_pin("vdd", "POWER")
         self.add_pin("gate", "INPUT")
+        self.add_pin("vdd", "POWER")
+        
 
     def create_instances(self):
         self.array_insts = []
@@ -164,7 +165,7 @@ class rom_precharge_array(design):
 
         # self.vdd = self.add_layout_pin_segment_center("vdd", self.supply_layer, start, end)
         # vdd = [self.pmos_insts[i].get_pin("vdd") for i in range(self.cols)]routeroute_horizon_horizon
-        self.route_horizontal_pins("vdd", insts=self.pmos_insts)
+        self.route_horizontal_pins("vdd", insts=self.pmos_insts, layer=self.strap_layer)
 
 
 

compiler/modules/rom_wordline_driver_array.py

@@ -86,11 +86,13 @@ class rom_wordline_driver_array(design):
         Add a pin for each row of vdd/gnd which
         are must-connects next level up.
         """
+
         if layer_props.wordline_driver.vertical_supply:
-            self.route_vertical_pins("vdd", self.wld_inst)
-            self.route_vertical_pins("gnd", self.wld_inst)
-            self.route_vertical_pins("vdd", self.wld_inst, layer=self.supply_layer)
-            self.route_vertical_pins("gnd", self.wld_inst, layer=self.supply_layer)
+            print("copied")
+            # self.route_vertical_pins("vdd", self.wld_inst)
+            # self.route_vertical_pins("gnd", self.wld_inst)
+            self.route_vertical_pins("vdd", [self], layer=self.supply_layer)
+            self.route_vertical_pins("gnd", [self], layer=self.supply_layer)
         else:
             self.route_vertical_pins("vdd", self.wld_inst, xside="rx",)
             self.route_vertical_pins("gnd", self.wld_inst, xside="lx",)
@@ -123,6 +125,8 @@ class rom_wordline_driver_array(design):
         route_width = drc["minwidth_{}".format(self.route_layer)]
         for row in range(self.rows):
             inst = self.wld_inst[row]
+            self.copy_layout_pin(inst, "vdd")
+            self.copy_layout_pin(inst, "gnd")
 
             self.copy_layout_pin(inst, "A", "in_{0}".format(row))