mirror of https://github.com/VLSIDA/OpenRAM.git
fixing decoder lvs
This commit is contained in:
Jacob Walker
parent
559300e5cc
commit
16df8e0e43
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@ -65,7 +65,9 @@ class rom_address_control_array(design):
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def add_pins(self):
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for col in range(self.cols):
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self.add_pin("A{0}_in".format(col), "INPUT")
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for col in range(self.cols):
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self.add_pin("A{0}_out".format(col), "OUTPUT")
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for col in range(self.cols):
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self.add_pin("Abar{0}_out".format(col), "OUTPUT")
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self.add_pin("clk", "INPUT")
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self.add_pin("vdd", "POWER")
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@ -117,7 +117,7 @@ class rom_base_array(bitcell_base_array):
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def add_pins(self):
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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self.add_pin(bl_name, "OUTPUT")
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("precharge_gate", "INPUT")
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@ -144,8 +144,12 @@ class rom_decoder(design):
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for i in range(self.num_inputs):
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control_pins.append("A{0}".format(i))
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control_pins.append("in_{0}".format(i))
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control_pins.append("inbar_{0}".format(i))
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for i in range(self.num_inputs):
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control_pins.append("A_int_{0}".format(i))
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for i in range(self.num_inputs):
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control_pins.append("Ab_int_{0}".format(i))
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control_pins.append("clk")
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control_pins.append("vdd")
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control_pins.append("gnd")
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@ -163,8 +167,8 @@ class rom_decoder(design):
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for i in reversed(range(self.num_inputs)):
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array_pins.append("inbar_{0}".format(i))
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array_pins.append("in_{0}".format(i))
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array_pins.append("Ab_int_{0}".format(i))
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array_pins.append("A_int_{0}".format(i))
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array_pins.append("precharge")
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array_pins.append("vdd")
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array_pins.append("gnd")
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@ -236,6 +240,7 @@ class rom_decoder(design):
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self.add_path(self.inv_route_layer, [addr_out_pin.center(), addr_middle, addr_pin.center()])
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self.add_path(self.inv_route_layer, [addr_bar_out_pin.center(), addr_bar_middle, addr_bar_pin.center()])
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self.copy_layout_pin(self.buf_inst, "A{}_in".format(i), "A{}".format(i))
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# self.add_segment_center(self.inv_route_layer, addr_bar_middle + vector(0, self.inv_route_width * 0.5), addr_bar_out_pin.center() + vector(0, self.inv_route_width * 0.5), self.inv_route_width)
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@ -250,42 +255,28 @@ class rom_decoder(design):
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self.copy_layout_pin(self.wordline_buf_inst, "gnd")
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self.copy_layout_pin(self.buf_inst, "gnd")
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# route decode array vdd and inv array vdd together
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# array_vdd = self.array_inst.get_pin("vdd")
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# inv_vdd = self.buf_inst.get_pins("vdd")[-1]
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# end = vector(array_vdd.cx(), inv_vdd.cy() - 0.5 * minwidth)
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# self.add_segment_center("m1", array_vdd.center(), end)
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# end = vector(array_vdd.cx() + 0.5 * minwidth, inv_vdd.cy())
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# self.add_segment_center(self.route_layer, inv_vdd.center(), end)
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# end = vector(array_vdd.cx(), inv_vdd.cy())
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# self.add_via_stack_center(end, self.route_layer, "m1")
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# self.add_layout_pin_rect_center("vdd", "m1", end)
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# Extend nwells to connect with eachother
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self.extend_wells()
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# # route pin on inv gnd
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# inv_gnd = self.buf_inst.get_pins("gnd")[0]
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# array_gnd = self.array_inst.get_pins("gnd")
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# # add x jog
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# start = vector(array_gnd[0].cx(), inv_gnd.cy())
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# self.add_via_stack_center(start, self.route_layer, "m1")
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# self.add_layout_pin_rect_center("gnd", "m1", start)
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# end = array_gnd[0].center()
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# self.add_segment_center("m1", start, end)
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# # add y jog
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def extend_wells(self):
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precharge_well_rx = self.array_inst.get_pins("vdd")[0].cx() + 0.5 * self.nwell_width
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precharge_well_lx = precharge_well_rx - self.array_mod.precharge_array.height - 0.5 * self.nwell_width - self.array_mod.precharge_array.well_offset
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# width = minwidth
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# height = array_gnd[0].uy() - array_gnd[-1].uy() + minwidth
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offset = vector(precharge_well_rx ,self.array_inst.by())
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# offset = vector(-0.5 *width ,0.5 * (array_gnd[0].cy() + array_gnd[-1].cy()))
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self.add_label(text="well_right", layer="nwell", offset=offset)
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offset = vector(precharge_well_lx ,self.array_inst.by())
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self.add_label(text="well_left", layer="nwell", offset=offset)
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vdd_pins=self.buf_inst.get_pins("vdd").copy()
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print(vdd_pins)
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well_by = vdd_pins[1].cy()
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well_ll = vector(precharge_well_lx, well_by)
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self.add_rect(layer="nwell", offset=well_ll, height = self.array_inst.by() - well_by, width=precharge_well_rx - precharge_well_lx)
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# start = end - vector(0, 0.5 * minwidth)
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# end = vector(start.x, array_gnd[1].uy())
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@ -175,6 +175,7 @@ class rom_precharge_array(design):
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self.connect_row_pins(layer=self.strap_layer, pins=array_pins, name=None, round=False)
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def extend_well(self):
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self.well_offset = self.pmos.tap_offset
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well_y = self.pmos_insts[0].get_pin("vdd").cy() - 0.5 * self.nwell_width
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well_y = self.get_pin("vdd").cy() - 0.5 * self.nwell_width
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@ -78,7 +78,7 @@ class rom_precharge_cell(rom_base_cell):
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source = self.cell_inst.get_pin("S")
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tap_y = source.cy() - self.contact_width - 2 * self.active_enclose_contact - self.active_space
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self.tap_offset = abs(tap_y)
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pos = vector(source.cx(), tap_y )
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self.add_via_center(layers=self.active_stack,
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@ -28,6 +28,12 @@ class rom_wordline_driver_array(design):
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self.cols = cols
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self.invert_outputs=invert_outputs
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self.tap_spacing = tap_spacing
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if OPTS.tech_name == "sky130":
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self.supply_layer = "m1"
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else:
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self.supply_layer = "m2"
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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@ -45,8 +51,8 @@ class rom_wordline_driver_array(design):
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self.place_drivers()
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self.route_layout()
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self.route_supplies()
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self.place_taps()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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# inputs to wordline_driver.
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@ -60,6 +66,7 @@ class rom_wordline_driver_array(design):
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def add_modules(self):
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b = factory.create(module_type="rom_base_cell")
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self.tap = factory.create(module_type="rom_poly_tap", add_tap = True)
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if self.invert_outputs:
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self.wl_driver = factory.create(module_type="pinv_dec",
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@ -67,19 +74,12 @@ class rom_wordline_driver_array(design):
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height=b.height,
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add_wells=False)
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self.wl_driver_tap = factory.create(module_type="pinv_dec",
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size=self.cols,
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add_wells=True)
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else:
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self.wl_driver = factory.create(module_type="pbuf_dec",
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size=self.cols,
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height=b.height,
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add_wells=False)
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self.wl_driver_tap = factory.create(module_type="pbuf_dec",
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size=self.cols,
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add_wells=True)
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print(self.wl_driver.height)
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print(self.wl_driver_tap.height)
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def route_supplies(self):
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"""
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@ -89,6 +89,8 @@ class rom_wordline_driver_array(design):
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if layer_props.wordline_driver.vertical_supply:
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self.route_vertical_pins("vdd", self.wld_inst)
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self.route_vertical_pins("gnd", self.wld_inst)
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self.route_vertical_pins("vdd", self.wld_inst, layer=self.supply_layer)
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self.route_vertical_pins("gnd", self.wld_inst, layer=self.supply_layer)
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else:
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self.route_vertical_pins("vdd", self.wld_inst, xside="rx",)
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self.route_vertical_pins("gnd", self.wld_inst, xside="lx",)
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@ -96,12 +98,8 @@ class rom_wordline_driver_array(design):
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def create_drivers(self):
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self.wld_inst = []
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for row in range(self.rows):
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if row % self.tap_spacing == 0:
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self.wld_inst.append(self.add_inst(name="wld{0}".format(row),
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mod=self.wl_driver_tap))
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else:
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self.wld_inst.append(self.add_inst(name="wld{0}".format(row),
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mod=self.wl_driver))
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self.wld_inst.append(self.add_inst(name="wld{0}".format(row),
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mod=self.wl_driver))
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self.connect_inst(["in_{0}".format(row),
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"out_{0}".format(row),
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"vdd", "gnd"])
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@ -109,13 +107,14 @@ class rom_wordline_driver_array(design):
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def place_drivers(self):
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y_offset = 0
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for row in range(self.rows):
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# These are flipped since we always start with an RBL on the bottom
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if row % self.tap_spacing == 0:
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y_offset += self.tap.pitch_offset
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offset = [0, y_offset]
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self.wld_inst[row].place(offset=offset)
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y_offset += self.wld_inst[row].height
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self.width = self.wl_driver.width
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self.height = self.wl_driver.height * self.rows
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@ -137,3 +136,46 @@ class rom_wordline_driver_array(design):
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end=end)
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self.add_layout_pin_rect_center(text="out_{}".format(row), layer=self.route_layer, offset=end - vector(0, 0.5 * route_width))
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def place_taps(self):
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for wl in range(0 , self.rows, self.tap_spacing):
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driver = self.wld_inst[wl]
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source_pin1 = driver.get_pins("vdd")[0]
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gnd_pin1 = driver.get_pins("gnd")[0]
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left_edge = driver.get_pin("Z").cy() - 0.5 * self.contact_width - self.active_enclose_contact - self.active_space - 0.5 * self.active_contact.width
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contact_pos = vector(source_pin1.cx(), left_edge)
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self.place_tap(contact_pos, "n")
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contact_pos = vector( gnd_pin1.cx(), left_edge)
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self.place_tap(contact_pos, "p")
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if not self.invert_outputs:
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source_pin2 = driver.get_pins("vdd")[1]
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gnd_pin2 = driver.get_pins("gnd")[1]
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contact_pos = vector(source_pin2.cx(), left_edge)
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self.place_tap(contact_pos, "n")
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contact_pos = vector( gnd_pin2.cx(), left_edge)
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self.place_tap(contact_pos, "p")
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def place_tap(self, offset, well_type):
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self.add_via_center(layers=self.active_stack,
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offset=offset,
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implant_type=well_type,
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well_type=well_type,
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directions="nonpref")
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self.add_via_stack_center(offset=offset,
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from_layer=self.active_stack[2],
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to_layer=self.supply_layer)
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if well_type == "p":
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pin = "gnd"
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else:
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pin = "vdd"
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self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset)
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@ -25,7 +25,7 @@ class rom_decoder_test(openram_test):
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debug.info(2, "Testing 2x4 decoder for rom cell")
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a = factory.create(module_type="rom_decoder", num_outputs=20, strap_spacing=2, cols=16)
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a = factory.create(module_type="rom_decoder", num_outputs=16, strap_spacing=4, cols=16)
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self.local_check(a)
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openram.end_openram()
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