mirror of https://github.com/VLSIDA/OpenRAM.git
Change rom_base_bank name and top pin names
This commit is contained in:
mrg
Jacob Walker
parent
d2b5be0130
commit
56e14113aa
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@ -72,7 +72,7 @@ from .replica_pbitcell import *
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from .row_cap_array import *
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from .row_cap_bitcell_1port import *
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from .row_cap_bitcell_2port import *
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from .rom_base_bank import *
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from .rom_bank import *
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from .sense_amp_array import *
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from .sense_amp import *
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from .tri_gate_array import *
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@ -7,14 +7,14 @@
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#
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import datetime
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from math import ceil, log, sqrt
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from math import ceil, log
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from openram.base import vector
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from openram.base import design
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from openram import OPTS, debug, print_time
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from openram import OPTS, print_time
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from openram.sram_factory import factory
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from openram.tech import drc, layer, parameter
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class rom_base_bank(design):
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class rom_bank(design):
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"""
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Rom data bank with row and column decoder + control logic
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@ -113,14 +113,14 @@ class rom_base_bank(design):
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def add_pins(self):
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self.add_pin("clk", "INPUT")
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self.add_pin("CS", "INPUT")
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self.add_pin("cs", "INPUT")
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for i in range(self.row_bits + self.col_bits):
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self.add_pin("addr_{}".format(i), "INPUT")
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self.add_pin("addr[{}]".format(i), "INPUT")
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out_pins = []
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for j in range(self.word_size):
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out_pins.append("rom_out_{}".format(j))
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out_pins.append("dout[{}]".format(j))
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self.add_pin_list(out_pins, "OUTPUT")
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self.add_pin("vdd", "POWER")
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@ -208,14 +208,14 @@ class rom_base_bank(design):
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bitlines = ["bl_{}".format(bl) for bl in range(self.cols)]
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wordlines = ["wl_{}".format(wl) for wl in range(self.rows)]
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addr_msb = ["addr_{}".format(addr + self.col_bits) for addr in range(self.row_bits)]
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addr_lsb = ["addr_{}".format(addr) for addr in range(self.col_bits)]
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addr_msb = ["addr[{}]".format(addr + self.col_bits) for addr in range(self.row_bits)]
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addr_lsb = ["addr[{}]".format(addr) for addr in range(self.col_bits)]
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select_lines = ["word_sel_{}".format(word) for word in range(self.words_per_row)]
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bitline_bar = ["bl_b_{}".format(bl) for bl in range(self.cols)]
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pre_buf_outputs = ["rom_out_prebuf_{}".format(bit) for bit in range(self.word_size)]
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outputs = ["rom_out_{}".format(bl) for bl in range(self.word_size)]
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outputs = ["dout[{}]".format(bl) for bl in range(self.word_size)]
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array_pins = bitlines + wordlines + prechrg + vdd + gnd
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@ -236,7 +236,7 @@ class rom_base_bank(design):
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self.connect_inst(row_decode_pins)
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self.control_inst = self.add_inst(name="rom_control", mod=self.control_logic)
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self.connect_inst(["clk", "CS", "precharge", "clk_int", "vdd", "gnd"])
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self.connect_inst(["clk", "cs", "precharge", "clk_int", "vdd", "gnd"])
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self.mux_inst = self.add_inst(name="rom_column_mux", mod=self.column_mux)
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self.connect_inst(col_mux_pins)
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@ -445,17 +445,17 @@ class rom_base_bank(design):
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def place_top_level_pins(self):
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self.copy_layout_pin(self.control_inst, "CS")
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self.copy_layout_pin(self.control_inst, "CS", "cs")
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self.copy_layout_pin(self.control_inst, "clk_in", "clk")
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for i in range(self.word_size):
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self.copy_layout_pin(self.output_inv_inst, "out_{}".format(i), "rom_out_{}".format(i))
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self.copy_layout_pin(self.output_inv_inst, "out_{}".format(i), "dout[{}]".format(i))
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for lsb in range(self.col_bits):
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name = "addr_{}".format(lsb)
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name = "addr[{}]".format(lsb)
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self.copy_layout_pin(self.col_decode_inst, "A{}".format(lsb), name)
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for msb in range(self.col_bits, self.row_bits + self.col_bits):
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name = "addr_{}".format(msb)
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name = "addr[{}]".format(msb)
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pin_num = msb - self.col_bits
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self.copy_layout_pin(self.decode_inst, "A{}".format(pin_num), name)
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@ -466,65 +466,3 @@ class rom_base_bank(design):
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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# """
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# Reads a hexadecimal file from a given directory to be used as the data written to the ROM
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# endian is either "big" or "little"
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# word_size is the number of bytes per word
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# sets the row and column size based on the size of binary input, tries to keep array as square as possible,
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# """
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# def read_binary(self, data_file, word_size=2, endian="big", scramble_bits=False):
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# # Read data as hexidecimal text file
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# hex_file = open(data_file, 'r')
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# hex_data = hex_file.read()
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# # Convert from hex into an int
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# data_int = int(hex_data, 16)
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# # Then from int into a right aligned, zero padded string
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# bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
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# # Then turn the string into a list of ints
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# bin_data = list(bin_string)
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# bin_data = [int(x) for x in bin_data]
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# # data size in bytes
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# data_size = len(bin_data) / 8
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# num_words = int(data_size / word_size)
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# bytes_per_col = sqrt(num_words)
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# self.words_per_row = int(ceil(bytes_per_col /(2*word_size)))
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# bits_per_row = self.words_per_row * word_size * 8
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# self.cols = bits_per_row
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# self.rows = int(num_words / (self.words_per_row))
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# chunked_data = []
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# for i in range(0, len(bin_data), bits_per_row):
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# row_data = bin_data[i:i + bits_per_row]
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# if len(row_data) < bits_per_row:
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# row_data = [0] * (bits_per_row - len(row_data)) + row_data
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# chunked_data.append(row_data)
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# # if endian == "big":
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# self.data = chunked_data
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# if scramble_bits:
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# scrambled_chunked = []
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# for row_data in chunked_data:
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# scambled_data = []
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# for bit in range(self.word_size):
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# for word in range(self.words_per_row):
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# scambled_data.append(row_data[bit + word * self.word_size])
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# scrambled_chunked.append(scambled_data)
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# self.data = scrambled_chunked
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# # self.data.reverse()
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# debug.info(1, "Read rom binary: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, num_words, self.cols, self.rows, self.words_per_row))
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@ -44,7 +44,7 @@ class rom():
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self.name = name
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import openram.modules.rom_base_bank as rom
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import openram.modules.rom_bank as rom
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self.r = rom(name, rom_config)
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@ -86,7 +86,7 @@ sram: $(WORKING_SRAM_STAMPS)
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@mkdir -p $*
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@python3 -u $(ROM_COMPILER) $(OPENRAM_OPTS) -o $* -p $(MACRO_DIR)/$* $(MACRO_DIR)/$< && touch $@
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.DELETE_ON_ERROR: $(STAMPS)
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.DELETE_ON_ERROR: $(WORKING_SRAM_STAMPS) $(WORKING_ROM_STAMPS)
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$(DIRS):
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@$(MAKE) --no-print-directory $@.ok
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@ -94,6 +94,8 @@ $(DIRS):
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.PHONY: $(DIRS)
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clean:
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rm -rf $(STAMPS)
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rm -rf $(DIRS)
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rm -rf $(WORKING_SRAM_STAMPS)
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rm -rf $(WORKING_ROM_STAMPS)
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rm -rf $(SRAM_DIRS)
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rm -rf $(ROM_DIRS)
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.PHONY: clean
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@ -3,5 +3,6 @@ tech_name = "sky130"
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nominal_corner_only = True
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#route_supplies = "ring"
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check_lvsdrc = True
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#check_lvsdrc = True
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check_lvsdrc = False
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