updated imports to match upstream dev openram

compiler/modules/rom_array_gnd_tap.py

@@ -1,8 +1,8 @@
 
 
-from base import design
-from base import vector
-from sram_factory import factory
+from openram.base import design
+from openram.base import vector
+from openram.sram_factory import factory
 
 class rom_array_gnd_tap(design):
 

compiler/modules/rom_base_array.py

@@ -9,11 +9,10 @@
 
 import math
 from .bitcell_base_array import bitcell_base_array
-from base import vector
-from globals import OPTS
-from sram_factory import factory
-import tech
-from tech import drc
+from openram.base import vector
+from openram import OPTS
+from openram.sram_factory import factory 
+from openram.tech import drc
 
 class rom_base_array(bitcell_base_array):
 

compiler/modules/rom_base_bank.py

@@ -1,11 +1,11 @@
 
 import math
-from base import vector
-from base import design
-from globals import OPTS
-from sram_factory import factory
+from openram.base import vector
+from openram.base import design
+from openram import OPTS
+from openram.sram_factory import factory
 import tech
-from tech import drc
+from openram.tech import drc
 
 class rom_base_bank(design):
 

compiler/modules/rom_base_cell.py

@@ -7,11 +7,10 @@
 #
 
 from .rom_dummy_cell import rom_dummy_cell
-from base import vector
-from globals import OPTS
-from sram_factory import factory
-
-from tech import drc
+from openram.base import vector
+from openram import OPTS
+from openram.sram_factory import factory
+from openram.tech import drc
 
 
 class rom_base_cell(rom_dummy_cell):

compiler/modules/rom_decoder.py

@@ -6,13 +6,12 @@
 # All rights reserved.
 #
 
-import math
-from base import design
-from sram_factory import factory
-from base import vector
-from globals import OPTS
-import tech
-from tech import drc
+from math import ceil, log
+from openram.base import design
+from openram.sram_factory import factory
+from openram.base import vector
+from openram import OPTS
+from openram.tech import drc
 
 
 class rom_decoder(design):
@@ -23,7 +22,7 @@ class rom_decoder(design):
         # array gets rotated 90deg so that rows/cols switch
         self.strap_spacing=strap_spacing
         self.num_outputs = num_outputs
-        self.num_inputs = math.ceil(math.log(num_outputs, 2))
+        self.num_inputs = ceil(log(num_outputs, 2))
         self.create_decode_map()
 
         for i in range(2 * self.num_inputs): print(self.decode_map[i])

compiler/modules/rom_dummy_cell.py

@@ -8,11 +8,11 @@
 
 
 
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
-from tech import drc
+from openram.base import design
+from openram.base import vector
+from openram import OPTS
+from openram.sram_factory import factory
+from openram.tech import drc
 
 
 class rom_dummy_cell(design):

compiler/modules/rom_inv_array.py

@@ -6,10 +6,10 @@
 # All rights reserved.
 #
 
-from base import design
-from sram_factory import factory
-from base import vector
-from tech import layer, drc
+from openram.base import design
+from openram.sram_factory import factory
+from openram.base import vector
+from openram.tech import layer, drc
 
 
 

compiler/modules/rom_poly_tap.py

@@ -1,9 +1,15 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
 
-
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram.base import design
+from openram.base import vector
+from openram import OPTS
+from openram.sram_factory import factory
 
 class rom_poly_tap(design):
 

compiler/modules/rom_precharge_array.py

@@ -6,12 +6,12 @@
 # All rights reserved.
 #
 
-import math
-from base import geometry
-from base import design
-from sram_factory import factory
-from base import vector
-from tech import layer, drc
+from math import ceil
+from openram.base import geometry
+from openram.base import design
+from openram.sram_factory import factory
+from openram.base import vector
+from openram.tech import layer, drc
 
 
 
@@ -40,7 +40,7 @@ class rom_precharge_array(design):
 
         
         if strap_spacing != 0:
-            self.num_straps = math.ceil(self.cols / self.strap_spacing)
+            self.num_straps = ceil(self.cols / self.strap_spacing)
             self.array_col_size = self.cols + self.num_straps  
         else:
             self.num_straps = 0

compiler/modules/rom_precharge_cell.py

@@ -6,12 +6,12 @@
 # All rights reserved.
 #
 
-from base import design
-from base import vector
-from globals import OPTS
-from sram_factory import factory
+from openram.base import design
+from openram.base import vector
+from openram import OPTS
+from openram.sram_factory import factory
 
-from tech import drc
+from openram.tech import drc
 
 
 class rom_precharge_cell(design):

compiler/tests/05_rom_array_test.py

@@ -6,21 +6,21 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import sys, os
 import unittest
 from testutils import *
-import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import debug
+from openram.sram_factory import factory
+from openram import OPTS
 
 
 class rom_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 4x4 array for rom cell")
 
@@ -29,11 +29,11 @@ class rom_array_test(openram_test):
 
         a = factory.create(module_type="rom_base_array", cols=9, rows=8, bitmap=data, strap_spacing=4)
         self.local_check(a)
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())

compiler/tests/05_rom_base_bank_test.py

@@ -10,9 +10,9 @@ import unittest
 from testutils import *
 import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
+import openram
+from openram import OPTS
+from openram.sram_factory import factory
 import debug
 
 
@@ -20,7 +20,7 @@ class rom_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 4x4 array for rom cell")
 
@@ -31,7 +31,7 @@ class rom_bank_test(openram_test):
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())

compiler/tests/05_rom_decoder_test.py

@@ -10,28 +10,28 @@ import unittest
 from testutils import *
 import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
-import debug
+import openram
+from openram import OPTS
+from openram.sram_factory import factory
+from openram import debug
 
 
 class rom_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 2x4 decoder for rom cell")
 
 
         a = factory.create(module_type="rom_decoder", num_outputs=8, strap_spacing=2)
         self.local_check(a)
-        globals.end_openram()
+        openram.end_openram()
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())

compiler/tests/05_rom_precharge_array_test.py

@@ -10,9 +10,9 @@ import unittest
 from testutils import *
 import sys, os
 
-import globals
-from globals import OPTS
-from sram_factory import factory
+import openram
+from openram import OPTS
+from openram.sram_factory import factory
 import debug
 
 
@@ -20,7 +20,7 @@ class rom_precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        openram.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing precharge array for rom cell")
 
@@ -31,7 +31,7 @@ class rom_precharge_test(openram_test):
 
 # run the test from the command line
 if __name__ == "__main__":
-    (OPTS, args) = globals.parse_args()
+    (OPTS, args) = openram.parse_args()
     del sys.argv[1:]
     header(__file__, OPTS.tech_name)
     unittest.main(testRunner=debugTestRunner())