mirror of https://github.com/VLSIDA/OpenRAM.git
convert 1-indexing to 0-indexing
This commit is contained in:
Sam Crow
parent
006eacd6d0
commit
28ea93bd0a
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@ -108,8 +108,8 @@ class control_logic_delay(control_logic_base):
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"""
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calculate the pinouts needed for the delay chain based on:
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wl driver delay, bl minus vth delay, precharge duration
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delays 1 & 2 need to be even for polarity
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delays 3 - 5 need to be odd for polarity
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delays 0 & 1 need to be even for polarity
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delays 2 - 4 need to be odd for polarity
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"""
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bitcell = factory.create(module_type=OPTS.bitcell)
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inverter_stage_delay = logical_effort("inv", 1, 1, OPTS.delay_chain_fanout_per_stage, 1, True).get_absolute_delay()
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@ -119,19 +119,19 @@ class control_logic_delay(control_logic_base):
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# FIXME: bad approximation?
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bitline_vth_delay = precharge_duration / 2
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delays = []
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delays = [None] * 5
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# hardcode 2 delay stages as keepout between p_en and wl_en
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delays[1] = 2
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delays[3] = delays[1] + precharge_duration / inverter_stage_delay
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delays[0] = 2
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delays[2] = delays[0] + precharge_duration / inverter_stage_delay
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# round up to nearest odd integer
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delays[3] = 1 - (2 * ((1 - delays[3]) // 2))
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# delays[2] can be any even value less than delays[3]
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delays[2] = delays[3] - 1
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delays[2] = 1 - (2 * ((1 - delays[2]) // 2))
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# delays[1] can be any even value less than delays[2]
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delays[1] = delays[2] - 1
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# hardcode 2 delay stages as keepout between p_en and wl_en
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delays[4] = delays[3] + 2
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delays[5] = delays[4] + bitline_vth_delay / inverter_stage_delay
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delays[3] = delays[2] + 2
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delays[4] = delays[3] + bitline_vth_delay / inverter_stage_delay
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# round up to nearest odd integer
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delays[5] = 1 - (2 * ((1 - delays[5]) // 2))
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delays[4] = 1 - (2 * ((1 - delays[4]) // 2))
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self.delay_chain_pinout_list = delays
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# FIXME: fanout should be used to control delay chain height
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# for now, use default/user-defined fanout constant
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@ -153,9 +153,9 @@ class control_logic_delay(control_logic_base):
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# list of output control signals (for making a vertical bus)
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if self.port_type == "rw":
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self.internal_bus_list = ["glitch2", "glitch3", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"]
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self.internal_bus_list = ["glitch1", "glitch2", "delay0", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "clk_buf", "cs"]
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else:
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self.internal_bus_list = ["glitch2", "glitch3", "delay1", "delay2", "delay3", "delay4", "delay5", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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self.internal_bus_list = ["glitch1", "glitch2", "delay0", "delay1", "delay2", "delay3", "delay4", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list) + 1) * self.m2_pitch
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@ -205,11 +205,11 @@ class control_logic_delay(control_logic_base):
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row += 1
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self.place_wlen_row(row)
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row += 1
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self.place_glitch2_row(row)
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self.place_glitch1_row(row)
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row += 1
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self.place_glitch3_row(row)
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self.place_glitch2_row(row)
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self.control_center_y = self.glitch3_nand_inst.uy() + self.m3_pitch
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self.control_center_y = self.glitch2_nand_inst.uy() + self.m3_pitch
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def route_all(self):
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""" Routing between modules """
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@ -232,36 +232,43 @@ class control_logic_delay(control_logic_base):
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""" Create the delay chain """
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self.delay_inst=self.add_inst(name="multi_delay_chain",
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mod=self.delay_chain)
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self.connect_inst(["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5", "vdd", "gnd"])
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self.connect_inst(["gated_clk_buf", "delay0", "delay1", "delay2", "delay3", "delay4", "vdd", "gnd"])
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def route_delay(self):
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# this is a bit of a hack because I would prefer to just name these pins delay in the layout
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# instead I have this which duplicates the out_pin naming logic from multi_delay_chain.py
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out_pins = ["out{}".format(str(pin)) for pin in self.delay_chain.pinout_list]
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delay_map = zip(["in", out_pins[0], out_pins[1], out_pins[2], out_pins[3], out_pins[4]], \
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["gated_clk_buf", "delay1", "delay2", "delay3", "delay4", "delay5"])
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["gated_clk_buf", "delay0", "delay1", "delay2", "delay3", "delay4"])
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self.connect_vertical_bus(delay_map,
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self.delay_inst,
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self.input_bus,
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self.m2_stack[::-1])
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# glitch{1-3} are internal timing signals based on different in/out
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# glitch{0-2} are internal timing signals based on different in/out
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# points on the delay chain for adjustable start time and duration
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def create_glitches(self):
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self.glitch0_nand_inst = self.add_inst(name="nand2_glitch0",
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mod=self.nand2)
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self.connect_inst(["delay0", "delay2", "glitch0", "vdd", "gnd"])
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self.glitch1_nand_inst = self.add_inst(name="nand2_glitch1",
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mod=self.nand2)
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self.connect_inst(["delay1", "delay3", "glitch1", "vdd", "gnd"])
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self.connect_inst(["gated_clk_buf", "delay3", "glitch1", "vdd", "gnd"])
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self.glitch2_nand_inst = self.add_inst(name="nand2_glitch2",
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mod=self.nand2)
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self.connect_inst(["gated_clk_buf", "delay4", "glitch2", "vdd", "gnd"])
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self.connect_inst(["delay1", "delay4", "glitch2", "vdd", "gnd"])
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self.glitch3_nand_inst = self.add_inst(name="nand2_glitch3",
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mod=self.nand2)
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self.connect_inst(["delay2", "delay5", "glitch3", "vdd", "gnd"])
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# glitch0 is placed in place_pen_row()
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# glitch1 is placed in place_pen_row()
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def place_glitch1_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row)
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self.row_end_inst.append(self.glitch1_nand_inst)
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def place_glitch2_row(self, row):
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x_offset = self.control_x_offset
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@ -270,26 +277,19 @@ class control_logic_delay(control_logic_base):
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self.row_end_inst.append(self.glitch2_nand_inst)
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def place_glitch3_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_nand_inst, x_offset, row)
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self.row_end_inst.append(self.glitch3_nand_inst)
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def route_glitches(self):
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glitch2_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay4", "glitch2"])
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glitch1_map = zip(["A", "B", "Z"], ["gated_clk_buf", "delay3", "glitch1"])
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self.connect_vertical_bus(glitch1_map, self.glitch1_nand_inst, self.input_bus)
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glitch2_map = zip(["A", "B", "Z"], ["delay1", "delay4", "glitch2"])
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self.connect_vertical_bus(glitch2_map, self.glitch2_nand_inst, self.input_bus)
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glitch3_map = zip(["A", "B", "Z"], ["delay2", "delay5", "glitch3"])
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self.connect_vertical_bus(glitch3_map, self.glitch3_nand_inst, self.input_bus)
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def create_wlen_row(self):
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self.wl_en_unbuf_and_inst = self.add_inst(name="and_wl_en_unbuf",
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mod=self.wl_en_and)
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self.connect_inst(["cs", "glitch2", "wl_en_unbuf", "vdd", "gnd"])
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self.connect_inst(["cs", "glitch1", "wl_en_unbuf", "vdd", "gnd"])
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self.wl_en_driver_inst=self.add_inst(name="buf_wl_en",
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mod=self.wl_en_driver)
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@ -304,7 +304,7 @@ class control_logic_delay(control_logic_base):
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self.row_end_inst.append(self.wl_en_driver_inst)
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def route_wlen(self):
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in_map = zip(["A", "B"], ["cs", "glitch2"])
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in_map = zip(["A", "B"], ["cs", "glitch1"])
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self.connect_vertical_bus(in_map, self.wl_en_unbuf_and_inst, self.input_bus)
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out_pin = self.wl_en_unbuf_and_inst.get_pin("Z")
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@ -321,21 +321,21 @@ class control_logic_delay(control_logic_base):
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def create_pen_row(self):
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self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar",
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mod=self.p_en_bar_driver)
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self.connect_inst(["glitch1", "p_en_bar", "vdd", "gnd"])
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self.connect_inst(["glitch0", "p_en_bar", "vdd", "gnd"])
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def place_pen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch1_nand_inst, x_offset, row)
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x_offset = self.place_util(self.glitch0_nand_inst, x_offset, row)
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x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row)
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self.row_end_inst.append(self.p_en_bar_driver_inst)
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def route_pen(self):
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in_map = zip(["A", "B"], ["delay1", "delay3"])
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self.connect_vertical_bus(in_map, self.glitch1_nand_inst, self.input_bus)
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in_map = zip(["A", "B"], ["delay0", "delay2"])
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self.connect_vertical_bus(in_map, self.glitch0_nand_inst, self.input_bus)
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out_pin = self.glitch1_nand_inst.get_pin("Z") # same code here as wl_en, refactor?
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out_pin = self.glitch0_nand_inst.get_pin("Z") # same code here as wl_en, refactor?
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out_pos = out_pin.center()
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in_pin = self.p_en_bar_driver_inst.get_pin("A")
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in_pos = in_pin.center()
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@ -355,7 +355,7 @@ class control_logic_delay(control_logic_base):
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self.s_en_gate_inst = self.add_inst(name="and_s_en",
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mod=self.sen_and3)
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self.connect_inst(["glitch3", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
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self.connect_inst(["glitch2", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
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def place_sen_row(self, row):
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x_offset = self.control_x_offset
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@ -371,15 +371,15 @@ class control_logic_delay(control_logic_base):
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else:
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input_name = "cs"
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sen_map = zip(["A", "B", "C"], ["glitch3", "gated_clk_bar", input_name])
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sen_map = zip(["A", "B", "C"], ["glitch2", "gated_clk_bar", input_name])
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self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.input_bus)
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self.connect_output(self.s_en_gate_inst, "Z", "s_en")
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def create_wen_row(self):
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self.glitch3_bar_inv_inst = self.add_inst(name="inv_glitch3_bar",
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self.glitch2_bar_inv_inst = self.add_inst(name="inv_glitch2_bar",
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mod=self.inv)
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self.connect_inst(["glitch3", "glitch3_bar", "vdd", "gnd"])
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self.connect_inst(["glitch2", "glitch2_bar", "vdd", "gnd"])
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if self.port_type == "rw":
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input_name = "we"
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@ -388,21 +388,21 @@ class control_logic_delay(control_logic_base):
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self.w_en_gate_inst = self.add_inst(name="and_w_en",
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mod=self.wen_and)
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self.connect_inst([input_name, "glitch2", "glitch3_bar", "w_en", "vdd", "gnd"])
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self.connect_inst([input_name, "glitch1", "glitch2_bar", "w_en", "vdd", "gnd"])
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def place_wen_row(self, row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.glitch3_bar_inv_inst, x_offset, row)
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x_offset = self.place_util(self.glitch2_bar_inv_inst, x_offset, row)
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x_offset = self.place_util(self.w_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.w_en_gate_inst)
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def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted
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glitch3_map = zip(["A"], ["glitch3"])
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self.connect_vertical_bus(glitch3_map, self.glitch3_bar_inv_inst, self.input_bus)
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glitch2_map = zip(["A"], ["glitch2"])
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self.connect_vertical_bus(glitch2_map, self.glitch2_bar_inv_inst, self.input_bus)
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out_pin = self.glitch3_bar_inv_inst.get_pin("Z")
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out_pin = self.glitch2_bar_inv_inst.get_pin("Z")
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out_pos = out_pin.center()
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in_pin = self.w_en_gate_inst.get_pin("C")
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in_pos = in_pin.center()
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@ -418,7 +418,7 @@ class control_logic_delay(control_logic_base):
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input_name = "cs"
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# This is the second gate over, so it needs to be on M3
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wen_map = zip(["A", "B"], [input_name, "glitch2"])
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wen_map = zip(["A", "B"], [input_name, "glitch1"])
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self.connect_vertical_bus(wen_map,
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self.w_en_gate_inst,
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self.input_bus,
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