mirror of https://github.com/VLSIDA/OpenRAM.git
place wl_en pin on wl drivers in absence of rbl_wl driver
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parent
0b5039cc89
commit
5b10f06be6
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@ -131,14 +131,16 @@ class port_address(design):
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offset=driver_in_pos)
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# Route the RBL from the enable input
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en_pin = self.wordline_driver_array_inst.get_pin("en")
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if self.port == 0:
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en_pos = en_pin.bc()
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else:
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en_pos = en_pin.uc()
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if self.has_rbl:
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en_pin = self.wordline_driver_array_inst.get_pin("en")
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if self.port == 0:
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en_pos = en_pin.bc()
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else:
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en_pos = en_pin.uc()
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rbl_in_pin = self.rbl_driver_inst.get_pin("A")
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rbl_in_pos = rbl_in_pin.center()
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wl_en_offset = rbl_in_pos
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self.add_via_stack_center(from_layer=rbl_in_pin.layer,
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to_layer=en_pin.layer,
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@ -147,9 +149,12 @@ class port_address(design):
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start=rbl_in_pos,
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end=en_pos,
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first_direction="V")
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self.add_layout_pin_rect_center(text="wl_en",
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layer=en_pin.layer,
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offset=rbl_in_pos)
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else:
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wl_en_offset = en_pos
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self.add_layout_pin_rect_center(text="wl_en",
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layer=en_pin.layer,
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offset=wl_en_offset)
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def add_modules(self):
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