mirror of https://github.com/VLSIDA/OpenRAM.git
Format fixes
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6eb0ecd82b
commit
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@ -1261,19 +1261,18 @@ class delay(simulation):
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def guess_spice_names(self):
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"""This is run in place of set_internal_spice_names function from
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simulation.py when running stand-alone characterizer."""
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# TODO: Find a better method
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with open(self.sp_file, "r") as file:
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bl_prefix = None
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br_prefix = None
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replica_bitcell_array_name = None
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for line in file:
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if re.search("bl_\d_\d", line):
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if re.search(r"bl_\d_\d", line):
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bl_prefix = "bl_"
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br_prefix = "br_"
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if re.search("bl\d_\d", line):
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if re.search(r"bl\d_\d", line):
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bl_prefix = "bl"
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br_prefix = "br"
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if re.search("Xreplica_bitcell_array", line):
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if re.search(r"Xreplica_bitcell_array", line):
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replica_bitcell_array_name = "replica_bitcell_array"
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if bl_prefix and replica_bitcell_array_name:
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break
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@ -1285,10 +1284,6 @@ class delay(simulation):
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replica_bitcell_array_name = "bitcell_array"
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self.cell_format = "X{{0}}{{3}}xbank0{{3}}x{0}{{3}}xbitcell_array{{3}}xbit_r{{1}}_c{{2}}".format(replica_bitcell_array_name)
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def analysis_init(self, probe_address, probe_data):
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"""Sets values which are dependent on the data address/bit being tested."""
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