mirror of https://github.com/VLSIDA/OpenRAM.git
code cleanup and updated copyright
This commit is contained in:
Jacob Walker
parent
ab955f0da8
commit
79efff9ca6
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@ -1,11 +1,10 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from openram.base import design
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from openram.sram_factory import factory
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from openram.base import vector
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@ -74,13 +73,12 @@ class rom_address_control_array(design):
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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self.buf_insts = []
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for col in range(self.cols):
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name = "Xaddr_buf_{0}".format(col)
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addr_buf = self.add_inst(name=name, mod=self.addr_control)
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A_in = "A{0}_in".format(col)
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@ -99,24 +97,16 @@ class rom_address_control_array(design):
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self.buf_insts[col].place(offset=base, mirror="MY")
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def copy_pins(self):
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for i in range(self.cols):
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self.copy_layout_pin(self.buf_insts[i], "A_out", "A{0}_out".format(i))
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self.copy_layout_pin(self.buf_insts[i], "Abar_out", "Abar{0}_out".format(i))
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self.copy_layout_pin(self.buf_insts[i], "A_in", "A{0}_in".format(i))
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def route_clk(self):
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self.route_horizontal_pins("clk", insts=self.buf_insts, layer=self.route_layer)
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def route_sources(self):
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self.route_horizontal_pins("vdd", insts=self.buf_insts, layer=self.route_layer)
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self.route_horizontal_pins("gnd", insts=self.buf_insts, layer=self.route_layer)
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self.route_horizontal_pins("gnd", insts=self.buf_insts, layer=self.route_layer)
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@ -1,6 +1,6 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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@ -22,10 +22,7 @@ class rom_address_control_buf(design):
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self.route_layer = route_layer
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self.add_wells = add_wells
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self.size = size
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if "li" in layer:
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self.inv_layer = "li"
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else:
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@ -39,7 +36,6 @@ class rom_address_control_buf(design):
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.width = self.cell.height * 2
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self.height = self.inv.width + 2 * self.nand.width
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@ -50,10 +46,8 @@ class rom_address_control_buf(design):
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self.route_sources()
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self.add_boundary()
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def create_modules(self):
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# self.inv1_mod = factory.create(module_type="pinv", module_name="inv_array_end_mod", height=self.inv_size, add_wells=False)
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self.inv = factory.create(module_type="pinv_dec", module_name="inv_array_mod", add_wells=False, size=self.size)
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# self.end_inv = factory.create(module_type="pinv", module_name="inv_array_end_mod", size=self.size, add_wells=True)
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@ -62,7 +56,7 @@ class rom_address_control_buf(design):
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self.cell = factory.create(module_type="rom_base_cell")
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def add_pins(self):
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self.add_pin("A_in", "INPUT")
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self.add_pin("A_out", "INOUT")
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self.add_pin("Abar_out", "OUTPUT")
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@ -83,7 +77,7 @@ class rom_address_control_buf(design):
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self.addr_nand = self.add_inst(name=name, mod=self.nand)
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inst_A = "clk"
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inst_B = "Abar_internal"
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inst_B = "Abar_internal"
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inst_Z = "A_out"
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self.connect_inst([inst_A, inst_B, inst_Z, "vdd", "gnd"])
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@ -95,39 +89,30 @@ class rom_address_control_buf(design):
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inst_Z = "Abar_out"
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self.connect_inst([inst_A, inst_B, inst_Z, "vdd", "gnd"])
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def setup_layout_constants(self):
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self.route_width = drc["minwidth_{}".format(self.route_layer)]
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self.interconnect_width = drc["minwidth_{}".format(self.inv_layer)]
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def place_instances(self):
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self.inv_inst.place(offset=vector(self.inv_inst.height,0), rotate=90)
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self.addr_nand.place(offset=vector(self.addr_nand.height , self.inv_inst.width + self.route_width ), rotate=90)
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self.addr_bar_nand.place(offset=vector( self.addr_bar_nand.height, self.addr_nand.width + self.inv_inst.width + self.route_width), rotate=90)
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def route_gates(self):
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clk1_pin = self.addr_nand.get_pin("A")
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clk2_pin = self.addr_bar_nand.get_pin("A")
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# self.add_label("HERE I AM", "poly", clk_pins.cl())
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Abar_out = self.addr_bar_nand.get_pin("Z")
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A_out = self.addr_nand.get_pin("Z")
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Abar_in = self.addr_nand.get_pin("B")
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Abar_int_out = self.inv_inst.get_pin("Z")
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Aint_in = self.addr_bar_nand.get_pin("B")
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A_in = self.inv_inst.get_pin("A")
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# Find the center of the pmos poly/gate
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poly_right = clk1_pin.cx() + self.poly_enclose_contact + 0.5 * self.contact_width
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@ -160,7 +145,7 @@ class rom_address_control_buf(design):
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self.add_layout_pin_rect_center("A_out", offset=vector(end.x, self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2")
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# Route second NAND to output pin
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# Route second NAND to output pin
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self.add_via_stack_center(Abar_out.center(), self.inv_layer, "m2")
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self.add_segment_center("m2", Abar_out.center(), vector(Abar_out.cx(), self.addr_bar_nand.uy()))
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self.add_layout_pin_rect_center("Abar_out", offset=vector(Abar_out.cx(), self.addr_bar_nand.uy() - 0.5 * self.m2_width), layer="m2")
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@ -170,9 +155,6 @@ class rom_address_control_buf(design):
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end = vector(Abar_int_out.cx(), Abar_in.cy() + 0.5 * self.interconnect_width)
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self.add_segment_center(self.inv_layer, Abar_int_out.center(), end)
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self.copy_layout_pin(self.inv_inst, "A", "A_in")
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def route_sources(self):
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@ -209,6 +191,4 @@ class rom_address_control_buf(design):
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well_type="p")
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self.add_via_stack_center(offset=contact_pos,
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from_layer=self.active_stack[2],
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to_layer=self.route_layer)
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to_layer=self.route_layer)
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@ -1,6 +1,6 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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@ -29,8 +29,6 @@ class rom_base_array(bitcell_base_array):
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self.data_col_size = self.column_size
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self.tap_spacing = tap_spacing
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if strap_spacing != 0:
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self.array_col_size = self.column_size + math.ceil(self.column_size / strap_spacing)
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else:
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@ -39,7 +37,6 @@ class rom_base_array(bitcell_base_array):
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self.create_all_wordline_names()
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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@ -47,14 +44,13 @@ class rom_base_array(bitcell_base_array):
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self.create_cell_instances()
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self.create_precharge_inst()
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def create_layout(self):
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self.create_layout_constants()
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self.place_array()
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if self.tap_direction == "row":
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self.route_pitch_offsets()
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self.place_precharge()
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self.place_wordline_contacts()
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self.place_bitline_contacts()
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@ -64,20 +60,15 @@ class rom_base_array(bitcell_base_array):
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self.place_rails()
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self.connect_taps()
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def add_boundary(self):
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ll = self.find_lowest_coords()
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m1_offset = self.m1_width
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self.translate_all(vector(0, ll.y + 0.5 * m1_offset))
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ur = self.find_highest_coords()
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ur = vector(ur.x, ur.y - self.m1_width)
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super().add_boundary(vector(0, 0), ur)
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self.width = ur.x
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self.height = ur.y
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def add_modules(self):
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@ -102,13 +93,10 @@ class rom_base_array(bitcell_base_array):
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strap_layer=self.wordline_layer,
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tap_direction=self.tap_direction)
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def create_layout_constants(self):
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self.route_width = drc("minwidth_" + self.bitline_layer)
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self.route_pitch = drc("{0}_to_{0}".format(self.bitline_layer))
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def add_pins(self):
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "OUTPUT")
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@ -123,7 +111,6 @@ class rom_base_array(bitcell_base_array):
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self.tap_list = []
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self.cell_inst = {}
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self.cell_list = []
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self.current_row = 0
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#list of current bitline interconnect nets, starts as the same as the bitline list and is updated when new insts of cells are added
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self.int_bl_list = self.bitline_names[0].copy()
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@ -133,21 +120,17 @@ class rom_base_array(bitcell_base_array):
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# for each new strap placed, offset the column index refrenced to get correct bit in the data array
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# cols are bit lines
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for col in range(self.column_size):
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if col % self.strap_spacing == 0:
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self.create_poly_tap(row, col)
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new_inst = self.create_cell(row, col)
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self.cell_inst[row, col] = new_inst
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row_list.append(new_inst)
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name = "tap_r{0}_c{1}".format(row, self.array_col_size)
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new_tap = self.add_inst(name=name, mod=self.poly_tap)
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self.tap_inst[row, self.column_size] = new_tap
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@ -155,10 +138,6 @@ class rom_base_array(bitcell_base_array):
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self.connect_inst([])
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self.cell_list.append(row_list)
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def create_poly_tap(self, row, col):
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name = "tap_r{0}_c{1}".format(row, col)
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@ -167,7 +146,6 @@ class rom_base_array(bitcell_base_array):
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self.tap_list.append(new_tap)
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self.connect_inst([])
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def create_cell(self, row, col):
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name = "bit_r{0}_c{1}".format(row, col)
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@ -182,7 +160,6 @@ class rom_base_array(bitcell_base_array):
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if self.data[row][col] == 1:
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self.int_bl_list[col] = "bl_int_{0}_{1}".format(row, col)
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bl_h = self.int_bl_list[col]
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# Final row of dummy nmos that contains only 1s, acts to prevent shorting bl to ground when precharging
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@ -198,23 +175,14 @@ class rom_base_array(bitcell_base_array):
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return new_inst
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def create_precharge_inst(self):
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prechrg_pins = self.bitline_names[0].copy()
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# for bl in range(self.column_size):
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# # if the internal bl was never updated there are no active cells in the bitline, so it should route straight to ground"
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# if self.int_bl_list[bl] == prechrg_pins[bl]:
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# prechrg_pins[bl] = "gnd"
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prechrg_pins.append("precharge")
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prechrg_pins.append("vdd")
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self.precharge_inst = self.add_inst(name="bitcell_array_precharge", mod=self.precharge_array)
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self.connect_inst(prechrg_pins)
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def create_all_bitline_names(self):
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for col in range(self.column_size):
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for port in self.all_ports:
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@ -222,37 +190,30 @@ class rom_base_array(bitcell_base_array):
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# Make a flat list too
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self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
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def place_rails(self):
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via_width = drc("m2_enclose_via1") * 0.5 + drc("minwidth_via1")
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pitch = drc["{0}_to_{0}".format(self.wordline_layer)]
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for i in range(self.column_size):
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drain = self.cell_list[self.row_size][i].get_pin("D")
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gnd_pos = drain.center() + vector(0, pitch + via_width + self.route_pitch)
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self.add_layout_pin_rect_center(text="gnd", layer=self.bitline_layer, offset=gnd_pos)
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self.route_horizontal_pins("gnd", insts=[self], yside="cy")
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self.copy_layout_pin(self.precharge_inst, "vdd")
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def place_array(self):
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self.cell_pos = {}
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self.strap_pos = {}
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# rows are wordlines
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pitch_offset = 0
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for row in range(self.row_size + 1):
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if row % self.tap_spacing == 0 and self.pitch_match and row != self.row_size:
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pitch_offset += self.active_contact.width + self.active_space
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cell_y = row * (self.zero_cell.height) + pitch_offset
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cell_x = 0
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for col in range(self.column_size):
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@ -262,19 +223,15 @@ class rom_base_array(bitcell_base_array):
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if self.tap_direction == "col":
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cell_x += self.poly_tap.pitch_offset
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self.cell_pos[row, col] = vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col])
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cell_x += self.zero_cell.width
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# self.add_label("debug", "li", self.cell_pos[row, col])
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self.strap_pos[row, self.column_size] = vector(cell_x, cell_y)
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self.tap_inst[row, self.column_size].place(self.strap_pos[row, self.column_size])
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def route_pitch_offsets(self):
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for row in range(0 , self.row_size, self.tap_spacing):
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@ -289,11 +246,8 @@ class rom_base_array(bitcell_base_array):
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start = vector(drain.cx(), source.cy())
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end = drain.center()
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self.add_segment_center(self.bitline_layer, start, end)
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self.place_well_tap(row, col)
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def place_well_tap(self, row, col):
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cell = self.cell_inst[row, col]
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source = cell.get_pin("S")
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@ -309,9 +263,7 @@ class rom_base_array(bitcell_base_array):
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else:
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tap_y = source.cy() - self.contact_width - 2 * self.active_enclose_contact - self.active_space
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tap_pos = vector(tap_x, tap_y)
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self.add_via_center(layers=self.active_stack,
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offset=tap_pos,
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implant_type="p",
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@ -322,27 +274,17 @@ class rom_base_array(bitcell_base_array):
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to_layer=self.wordline_layer)
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self.add_layout_pin_rect_center("gnd", self.wordline_layer, tap_pos)
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def place_precharge(self):
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self.precharge_offset = vector(0, - self.precharge_inst.height - self.zero_cell.nmos.end_to_contact - 2 * drc["nwell_enclose_active"] - 3 * self.m1_pitch)
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self.precharge_inst.place(offset=self.precharge_offset)
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self.copy_layout_pin(self.precharge_inst, "vdd")
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self.copy_layout_pin(self.precharge_inst, "gate", "precharge")
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|
||||
def place_wordline_contacts(self):
|
||||
|
||||
for wl in range(self.row_size):
|
||||
|
||||
self.copy_layout_pin(self.tap_inst[wl, 0], "poly_tap", self.wordline_names[0][wl])
|
||||
# self.add_via_stack_center(poly_via.center(), "m1", self.output_layer)
|
||||
|
||||
# self.create_horizontal_pin_bus(self.route_layer, offset=corrected_offset, names=self.wordline_names[0], pitch=self.zero_cell.height, length=None)
|
||||
|
||||
def place_bitline_contacts(self):
|
||||
|
||||
|
|
@ -361,11 +303,9 @@ class rom_base_array(bitcell_base_array):
|
|||
output_pos = vector(corrected.x, rail_y)
|
||||
|
||||
self.add_segment_center(self.bitline_layer, corrected, output_pos)
|
||||
|
||||
|
||||
self.add_layout_pin_rect_center(self.bitline_names[0][bl], self.bitline_layer, output_pos )
|
||||
|
||||
|
||||
|
||||
def route_precharge(self):
|
||||
for bl in range(self.column_size):
|
||||
bl_pin = self.cell_list[0][bl].get_pin("S")
|
||||
|
|
@ -376,7 +316,7 @@ class rom_base_array(bitcell_base_array):
|
|||
bl_end = vector(bl_start.x, pre_out_pin.cy())
|
||||
|
||||
self.add_segment_center(self.bitline_layer, bl_start, bl_end)
|
||||
|
||||
|
||||
upper_precharge = self.precharge_inst.get_pin("precharge_r")
|
||||
lower_precharge = self.tap_inst[self.row_size, self.column_size ].get_pin("poly_tap")
|
||||
|
||||
|
|
@ -388,13 +328,11 @@ class rom_base_array(bitcell_base_array):
|
|||
end = lower_precharge.center()
|
||||
mid1 = start + vector(wire_offset, 0)
|
||||
mid2 = end + vector(wire_offset, 0)
|
||||
|
||||
|
||||
self.add_path(layer="m1", coordinates=[start, mid1, mid2, end])
|
||||
|
||||
self.add_layout_pin_rect_center(text="precharge_r", layer="m1", offset=mid1)
|
||||
|
||||
|
||||
|
||||
def connect_taps(self):
|
||||
array_pins = [self.tap_list[i].get_pin("poly_tap") for i in range(len(self.tap_list))]
|
||||
|
||||
|
|
@ -404,8 +342,6 @@ class rom_base_array(bitcell_base_array):
|
|||
if self.tap_direction == "col":
|
||||
self.route_vertical_pins("active_tap", insts=self.tap_list, layer=self.supply_stack[0], full_width=False)
|
||||
|
||||
|
||||
|
||||
def get_next_cell_in_bl(self, row_start, col):
|
||||
for row in range(row_start + 1, self.row_size):
|
||||
if self.data[row][col] == 1:
|
||||
|
|
@ -421,6 +357,4 @@ class rom_base_array(bitcell_base_array):
|
|||
def create_next_bl_interconnect(self, row, col):
|
||||
"""create a new net name for a bitline interconnect"""
|
||||
self.current_row = row
|
||||
return "bli_{0}_{1}".format(row, col)
|
||||
|
||||
|
||||
return "bli_{0}_{1}".format(row, col)
|
||||
|
|
@ -1,3 +1,10 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
from math import ceil, log, sqrt
|
||||
from openram.base import vector
|
||||
|
|
@ -103,24 +110,7 @@ class rom_base_bank(design):
|
|||
# self.data.reverse()
|
||||
|
||||
debug.info(1, "Read rom binary: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, num_words, self.cols, self.rows, self.words_per_row))
|
||||
# self.print_data(chunked_data)
|
||||
# print("Scrambled")
|
||||
# self.print_data(scrambled_chunked)
|
||||
|
||||
# self.print_word(self.data, 0, 0)
|
||||
# self.print_word(self.data, 0, 1)
|
||||
# self.print_word(self.data, 0, 2)
|
||||
# self.print_word(self.data, 0, 3)
|
||||
# print("hex: {0}, binary: {1}, chunked: {2}".format(hex_data, bin_data, chunked_data))
|
||||
|
||||
def print_data(self, data_array):
|
||||
for row in range(len(data_array)):
|
||||
print(data_array[row])
|
||||
|
||||
def print_word(self, data_array, bl, word):
|
||||
for bit in range(self.word_size):
|
||||
print(data_array[bl][word + self.words_per_row * bit], end =" ")
|
||||
print("")
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_modules()
|
||||
|
|
@ -129,18 +119,13 @@ class rom_base_bank(design):
|
|||
|
||||
|
||||
def create_layout(self):
|
||||
print("Creating ROM bank instances")
|
||||
self.create_instances()
|
||||
print("Placing ROM bank instances")
|
||||
self.place_instances()
|
||||
|
||||
print("Routing decoders to array")
|
||||
self.route_decode_outputs()
|
||||
|
||||
print("Routing precharge signal")
|
||||
self.route_precharge()
|
||||
|
||||
print("Routing clock signal")
|
||||
self.route_clock()
|
||||
self.route_array_outputs()
|
||||
self.place_top_level_pins()
|
||||
|
|
@ -177,7 +162,6 @@ class rom_base_bank(design):
|
|||
|
||||
def add_modules(self):
|
||||
|
||||
print("Creating bank modules")
|
||||
# TODO: provide technology-specific calculation of these parameters
|
||||
# in sky130 the address control buffer is composed of 2 size 2 NAND gates,
|
||||
# with a beta of 3, each of these gates has gate capacitance of 2 min sized inverters, therefor a load of 4
|
||||
|
|
@ -487,16 +471,7 @@ class rom_base_bank(design):
|
|||
|
||||
channel_ll = vector( route_nets[0][0].cx(), route_nets[0][1].cy() + self.m1_pitch * 3)
|
||||
self.create_horizontal_channel_route(netlist=route_nets, offset=channel_ll, layer_stack=self.m1_stack)
|
||||
# for bit in range(self.word_size):
|
||||
# mux_pin = self.mux_inst.get_pin("bl_out_{}".format(bit))
|
||||
# buf_pin = self.output_buf_inst.get_pin("in_{}".format(bit))
|
||||
# mux_out = vector(mux_pin.cx(), mux_pin.by())
|
||||
# buf_in = buf_pin.center()
|
||||
|
||||
# mid1 = vector(mux_out.x, buf_in.y + bit * self.m2_pitch)
|
||||
# mid2 = vector(buf_in.x, mid1.y)
|
||||
# print("start: {0}, mid: {1}, stop: {2}".format(mux_out, mid1, buf_in))
|
||||
# self.add_path(layer="m2", coordinates=[mux_out, mid1, mid2, buf_in])
|
||||
|
||||
|
||||
|
||||
|
|
@ -523,13 +498,4 @@ class rom_base_bank(design):
|
|||
for inst in self.insts:
|
||||
if not inst.mod.name.__contains__("contact"):
|
||||
self.copy_layout_pin(inst, "vdd")
|
||||
self.copy_layout_pin(inst, "gnd")
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
self.copy_layout_pin(inst, "gnd")
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -80,7 +80,7 @@ class rom_base_cell(design):
|
|||
# height = self.base_width - min(self.cell_diffusion_offset, 0) - min(self.poly_active_offset, 0) - min(self.poly_tap_offset, 0)
|
||||
|
||||
# make the cells square so the pitch of wordlines will match bitlines
|
||||
# print("height: {0} width: {1}".format(height, width))
|
||||
|
||||
if width > height:
|
||||
self.width = width
|
||||
self.height = width
|
||||
|
|
@ -150,23 +150,4 @@ class rom_base_cell(design):
|
|||
|
||||
def short_gate(self):
|
||||
|
||||
self.add_segment_center(self.bitline_layer, self.get_pin("D").center(), self.get_pin("S").center())
|
||||
|
||||
# def place_tap(self):
|
||||
|
||||
# tap_x = self.poly_contact.width * 0.5
|
||||
# tap_y = self.via.uy() + drc["{0}_to_{0}".format(self.strap_layer)] * 2
|
||||
|
||||
# contact_pos = vector(tap_x, tap_y)
|
||||
# self.add_via_center(layers=self.active_stack,
|
||||
# offset=contact_pos,
|
||||
# implant_type="p",
|
||||
# well_type="p")
|
||||
# self.add_power_pin(name="gnd",
|
||||
# loc=contact_pos,
|
||||
# start_layer=self.active_stack[2])
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
self.add_segment_center(self.bitline_layer, self.get_pin("D").center(), self.get_pin("S").center())
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2022 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -207,11 +207,4 @@ class rom_column_mux(pgate):
|
|||
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer=self.supply_stack[0],
|
||||
offset=active_pos)
|
||||
|
||||
# Add well enclosure over all the tx and contact
|
||||
# if "pwell" in layer:
|
||||
# self.add_rect(layer="pwell",
|
||||
# offset=vector(0, 0),
|
||||
# width=rbc_width,
|
||||
# height=self.height)
|
||||
offset=active_pos)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2022 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -218,4 +218,4 @@ class rom_column_mux_array(design):
|
|||
"""
|
||||
for i in range(len(self.mux_inst)):
|
||||
if i != column_include_num:
|
||||
self.graph_inst_exclude.add(self.mux_inst[i])
|
||||
self.graph_inst_exclude.add(self.mux_inst[i])
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2022 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -28,7 +28,6 @@ class rom_control_logic(design):
|
|||
|
||||
self.clk_fanout = clk_fanout
|
||||
|
||||
|
||||
if "li" in layer:
|
||||
self.route_stack = self.li_stack
|
||||
else:
|
||||
|
|
@ -37,7 +36,6 @@ class rom_control_logic(design):
|
|||
self.create_netlist()
|
||||
self.create_layout()
|
||||
self.add_boundary()
|
||||
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_modules()
|
||||
|
|
@ -67,8 +65,7 @@ class rom_control_logic(design):
|
|||
fanout=self.output_size,
|
||||
height=self.driver_height,
|
||||
add_wells=True)
|
||||
|
||||
|
||||
|
||||
def add_pins(self):
|
||||
self.add_pin("clk_in", "INPUT")
|
||||
self.add_pin("CS", "INPUT")
|
||||
|
|
@ -90,17 +87,14 @@ class rom_control_logic(design):
|
|||
|
||||
|
||||
def place_instances(self):
|
||||
# nand_y = self.buf_inst.get_pin("vdd").cy() - self.nand_inst.get_pin("vdd").cy()
|
||||
self.nand_inst.place(offset=[self.buf_inst.width, 0])
|
||||
self.driver_inst.place(offset=[0, self.buf_inst.height + self.driver_inst.height], mirror="MX")
|
||||
|
||||
offset = self.driver_inst.get_pin("vdd").cy() - self.nand_inst.get_pin("vdd").cy()
|
||||
print("offset: {}".format(offset))
|
||||
self.driver_inst.place(offset=[0, self.buf_inst.height + self.driver_inst.height - offset], mirror="MX")
|
||||
|
||||
|
||||
def route_insts(self):
|
||||
|
||||
|
||||
route_width = drc["minwidth_{}".format(self.route_stack[2])]
|
||||
self.copy_layout_pin(self.buf_inst, "A", "clk_in")
|
||||
self.copy_layout_pin(self.buf_inst, "Z", "clk_out")
|
||||
|
|
@ -114,7 +108,7 @@ class rom_control_logic(design):
|
|||
|
||||
nand_B = self.nand_inst.get_pin("B")
|
||||
|
||||
|
||||
|
||||
# Connect buffered clock bar to nand input
|
||||
|
||||
mid = vector(clk.lx() - route_width - 2 * self.m1_space)
|
||||
|
|
@ -137,11 +131,10 @@ class rom_control_logic(design):
|
|||
|
||||
self.add_path(self.route_stack[2], [nand_Z.center(), mid, driver_A.center()])
|
||||
|
||||
|
||||
self.add_via_stack_center(from_layer=nand_Z.layer,
|
||||
to_layer=self.route_stack[2],
|
||||
offset=nand_Z.center())
|
||||
|
||||
|
||||
self.add_via_stack_center(from_layer=driver_A.layer,
|
||||
to_layer=self.route_stack[2],
|
||||
offset=driver_A.center())
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -11,11 +11,9 @@ from openram.base import vector, design
|
|||
from openram import OPTS
|
||||
from openram.tech import drc
|
||||
|
||||
|
||||
|
||||
class rom_decoder(design):
|
||||
def __init__(self, num_outputs, fanout, strap_spacing, name="", route_layer="m1", output_layer="m1", invert_outputs=False):
|
||||
|
||||
|
||||
# word lines/ rows / inputs in the base array become the address lines / cols / inputs in the decoder
|
||||
# bit lines / cols / outputs in the base array become the word lines / rows / outputs in the decoder
|
||||
# array gets rotated 90deg so that rows/cols switch
|
||||
|
|
@ -23,8 +21,6 @@ class rom_decoder(design):
|
|||
self.num_outputs = num_outputs
|
||||
self.num_inputs = ceil(log(num_outputs, 2))
|
||||
self.create_decode_map()
|
||||
|
||||
# for i in range(2 * self.num_inputs): print(self.decode_map[i])
|
||||
|
||||
super().__init__(name)
|
||||
|
||||
|
|
@ -45,7 +41,6 @@ class rom_decoder(design):
|
|||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
|
||||
def create_layout(self):
|
||||
self.setup_layout_constants()
|
||||
|
|
@ -57,13 +52,13 @@ class rom_decoder(design):
|
|||
self.connect_inputs()
|
||||
self.route_supplies()
|
||||
self.add_boundary()
|
||||
|
||||
|
||||
def add_boundary(self):
|
||||
ll = self.find_lowest_coords()
|
||||
m1_offset = self.m1_width
|
||||
self.translate_all(vector(0, ll.y))
|
||||
ur = self.find_highest_coords()
|
||||
|
||||
|
||||
ur = vector(ur.x, ur.y)
|
||||
super().add_boundary(ll, ur)
|
||||
self.width = ur.x
|
||||
|
|
@ -77,7 +72,7 @@ class rom_decoder(design):
|
|||
# create decoding map that will be the bitmap for the rom decoder
|
||||
# row/col order in the map will be switched in the placed decoder/
|
||||
for col in range(self.num_inputs):
|
||||
|
||||
|
||||
# odd cols are address
|
||||
# even cols are address bar
|
||||
col_array = []
|
||||
|
|
@ -93,18 +88,14 @@ class rom_decoder(design):
|
|||
bin_digit = int(addr[addr_idx])
|
||||
|
||||
col_array.append(bin_digit)
|
||||
# print("addr {0}, at indx {1}, digit {2}".format(addr, addr_idx, bin_digit))
|
||||
|
||||
if bin_digit == 0 : inv_col_array.append(1)
|
||||
else : inv_col_array.append(0)
|
||||
|
||||
|
||||
|
||||
self.decode_map.append(col_array)
|
||||
self.decode_map.append(inv_col_array)
|
||||
self.decode_map.reverse()
|
||||
|
||||
|
||||
def add_pins(self):
|
||||
for i in range(self.num_inputs):
|
||||
self.add_pin("A{0}".format(i), "INPUT")
|
||||
|
|
@ -116,20 +107,17 @@ class rom_decoder(design):
|
|||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
|
||||
def add_modules(self):
|
||||
|
||||
self.control_array = factory.create(module_type="rom_address_control_array",
|
||||
cols=self.num_inputs)
|
||||
|
||||
|
||||
self.wordline_buf = factory.create(module_type="rom_wordline_driver_array", module_name="{}_wordline_buffer".format(self.name),
|
||||
rows=self.num_outputs,
|
||||
fanout=ceil(self.fanout),
|
||||
invert_outputs=self.invert_outputs,
|
||||
tap_spacing=self.strap_spacing)
|
||||
|
||||
|
||||
self.array_mod = factory.create(module_type="rom_base_array",
|
||||
module_name="{}_array".format(self.name),
|
||||
cols=self.num_outputs,
|
||||
|
|
@ -139,13 +127,11 @@ class rom_decoder(design):
|
|||
bitline_layer=self.output_layer,
|
||||
tap_direction="col")
|
||||
|
||||
|
||||
def create_instances(self):
|
||||
|
||||
self.create_array_inst()
|
||||
self.create_input_buffer()
|
||||
self.create_wordline_buffer()
|
||||
|
||||
|
||||
def create_input_buffer(self):
|
||||
name = "pre_control_array"
|
||||
|
|
@ -159,17 +145,16 @@ class rom_decoder(design):
|
|||
control_pins.append("A_int_{0}".format(i))
|
||||
for i in range(self.num_inputs):
|
||||
control_pins.append("Ab_int_{0}".format(i))
|
||||
|
||||
|
||||
|
||||
|
||||
control_pins.append("clk")
|
||||
control_pins.append("vdd")
|
||||
control_pins.append("gnd")
|
||||
self.connect_inst(control_pins)
|
||||
|
||||
|
||||
def create_array_inst(self):
|
||||
self.array_inst = self.add_inst(name="decode_array_inst", mod=self.array_mod)
|
||||
|
||||
|
||||
array_pins = []
|
||||
|
||||
for j in range(self.num_outputs):
|
||||
|
|
@ -192,8 +177,6 @@ class rom_decoder(design):
|
|||
pwr_pins = ["vdd", "gnd"]
|
||||
self.connect_inst(in_pins + out_pins + pwr_pins)
|
||||
|
||||
|
||||
|
||||
def place_input_buffer(self):
|
||||
wl = self.array_mod.row_size - 1
|
||||
align = self.array_inst.get_pin(self.array_mod.wordline_names[0][wl]).cx() - self.buf_inst.get_pin("A0_out").cx()
|
||||
|
|
@ -202,12 +185,10 @@ class rom_decoder(design):
|
|||
|
||||
self.copy_layout_pin(self.buf_inst, "clk")
|
||||
|
||||
|
||||
|
||||
def place_array(self):
|
||||
offset = vector(self.array_mod.height, self.control_array.height + self.m1_width + self.poly_contact.width)
|
||||
self.array_inst.place(offset, rotate=90)
|
||||
|
||||
|
||||
def place_driver(self):
|
||||
|
||||
offset = vector(self.array_inst.height + self.m1_width, self.array_inst.by())
|
||||
|
|
@ -231,7 +212,6 @@ class rom_decoder(design):
|
|||
route_pins = array_pins + driver_pins
|
||||
self.connect_row_pins(self.output_layer, route_pins, round=True)
|
||||
|
||||
|
||||
def connect_inputs(self):
|
||||
|
||||
self.copy_layout_pin(self.array_inst, "precharge")
|
||||
|
|
@ -263,28 +243,4 @@ class rom_decoder(design):
|
|||
|
||||
self.copy_layout_pin(self.array_inst, "gnd")
|
||||
self.copy_layout_pin(self.wordline_buf_inst, "gnd")
|
||||
self.copy_layout_pin(self.buf_inst, "gnd")
|
||||
|
||||
# Extend nwells to connect with eachother
|
||||
# self.extend_wells()
|
||||
|
||||
|
||||
def extend_wells(self):
|
||||
precharge_well_rx = self.array_inst.get_pins("vdd")[0].cx() + 0.5 * self.nwell_width
|
||||
precharge_well_lx = precharge_well_rx - self.array_mod.precharge_array.height - 0.5 * self.nwell_width - self.array_mod.precharge_array.well_offset
|
||||
|
||||
|
||||
offset = vector(precharge_well_rx ,self.array_inst.by())
|
||||
|
||||
self.add_label(text="well_right", layer="nwell", offset=offset)
|
||||
offset = vector(precharge_well_lx ,self.array_inst.by())
|
||||
self.add_label(text="well_left", layer="nwell", offset=offset)
|
||||
vdd_pins=self.buf_inst.get_pins("vdd").copy()
|
||||
print(vdd_pins)
|
||||
well_by = vdd_pins[0].cy()
|
||||
# well_ll = vector(precharge_well_lx, well_by)
|
||||
well_ll = vector(self.buf_inst.rx(), well_by)
|
||||
# self.add_rect(layer="nwell", offset=well_ll, height = self.array_inst.by() - well_by, width=precharge_well_rx - self.buf_inst.rx())
|
||||
|
||||
|
||||
|
||||
self.copy_layout_pin(self.buf_inst, "gnd")
|
||||
|
|
@ -1,87 +0,0 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
from openram.base import design
|
||||
from openram.base import vector
|
||||
from openram import OPTS
|
||||
from openram.sram_factory import factory
|
||||
from openram.tech import drc
|
||||
|
||||
|
||||
class rom_dummy_cell(design):
|
||||
|
||||
def __init__(self, name="", cell_name=None, add_source_contact=False, add_drain_contact=False, route_layer="m1"):
|
||||
super().__init__(name, cell_name)
|
||||
self.route_layer = route_layer
|
||||
self.add_source_contact="li"
|
||||
self.add_drain_contact="li"
|
||||
self.create_netlist()
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
#creates nmos for layout dimensions
|
||||
self.add_nmos()
|
||||
|
||||
#set height and width such that the cell will tile perfectly by only ofsetting in the array by its width and height
|
||||
|
||||
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
|
||||
self.setup_drc_offsets()
|
||||
|
||||
self.add_boundary()
|
||||
self.add_poly()
|
||||
self.add_metal()
|
||||
#self.add_label("0,0", self.route_layer)
|
||||
|
||||
|
||||
|
||||
def add_poly(self):
|
||||
|
||||
poly_x = 0.5 * (self.nmos.poly_height + self.poly_extend_active_spacing)
|
||||
# 0.5 * self.nmos.contact_width + self.contact_to_gate
|
||||
|
||||
self.poly = self.add_rect_center("poly", vector(poly_x, self.base_width * 0.5), 2 * poly_x, self.poly_width)
|
||||
|
||||
def add_metal(self):
|
||||
|
||||
if self.route_layer == "li":
|
||||
via = "mcon"
|
||||
else:
|
||||
via = "via{}".format(self.route_layer[len(self.route_layer) - 1])
|
||||
wire_y = self.height + drc["minwidth_{}".format(via)] * 0.5
|
||||
wire_x = 0.5 * (self.width - self.poly_extend_active_spacing)
|
||||
|
||||
wire_start = vector( wire_x, 0)
|
||||
wire_end = vector(wire_x, wire_y)
|
||||
|
||||
# if self.route_layer == 'm1':
|
||||
|
||||
# if self.drain_contact:
|
||||
# self.add_via_center(self.li_stack, [wire_x, wire_y])
|
||||
# if self.source_contact:
|
||||
# self.add_via_center(self.li_stack, [self.width, wire_y])
|
||||
|
||||
self.add_path(self.route_layer, [wire_start, wire_end])
|
||||
|
||||
# drain_x = 0
|
||||
# drain_y = 0.5 * (self.width)
|
||||
source_x = 0.5 * (self.width - self.poly_extend_active_spacing)
|
||||
source_y = 0
|
||||
source_pos = vector(source_x, source_y)
|
||||
self.add_layout_pin_rect_center("S", self.route_layer, source_pos)
|
||||
|
||||
drain_pos = vector(source_x, self.height)
|
||||
self.add_layout_pin_rect_center("D", self.route_layer, drain_pos)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,11 +1,10 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
from openram.base import design
|
||||
from openram.base import vector
|
||||
from openram import OPTS
|
||||
|
|
@ -27,11 +26,6 @@ class rom_poly_tap(design):
|
|||
#for layout constants
|
||||
self.dummy = factory.create(module_type="rom_base_cell")
|
||||
|
||||
# if self.tx_type == "nmos":
|
||||
# self.dummy = factory.create(module_type="rom_base_cell")
|
||||
# else:
|
||||
# self.dummy = factory.create(module_type="rom_precharge_cell")
|
||||
|
||||
self.pmos = factory.create(module_type="ptx", tx_type="pmos")
|
||||
|
||||
def create_layout(self):
|
||||
|
|
@ -41,12 +35,7 @@ class rom_poly_tap(design):
|
|||
if self.add_tap:
|
||||
self.place_active_tap()
|
||||
self.extend_poly()
|
||||
|
||||
|
||||
# if self.length != 0:
|
||||
# self.place_strap()
|
||||
|
||||
|
||||
def add_boundary(self):
|
||||
contact_width = self.poly_contact.width
|
||||
|
||||
|
|
@ -57,7 +46,7 @@ class rom_poly_tap(design):
|
|||
super().add_boundary()
|
||||
|
||||
def place_via(self):
|
||||
|
||||
|
||||
contact_width = self.poly_contact.width
|
||||
|
||||
# DRC rule here is hard coded since licon.9 isnt included in skywater130 tech file
|
||||
|
|
@ -71,7 +60,7 @@ class rom_poly_tap(design):
|
|||
contact_y = self.dummy.cell_inst.width * 0.5 - 0.5 * self.contact_width - self.active_enclose_contact
|
||||
|
||||
if self.tx_type == "nmos":
|
||||
|
||||
|
||||
# contact_y = self.dummy.cell_inst.width * 0.5 - 0.5 * self.contact_width - self.active_enclose_contact
|
||||
# contact_y = self.dummy.poly.offset.x + (self.poly_width * 0.5)
|
||||
self.contact_x_offset = 0
|
||||
|
|
@ -86,15 +75,6 @@ class rom_poly_tap(design):
|
|||
offset=self.contact_offset)
|
||||
self.add_layout_pin_rect_center("poly_tap", self.strap_layer, self.contact_offset)
|
||||
|
||||
|
||||
# def place_strap(self):
|
||||
|
||||
# strap_start = vector(self.via.lx() , self.via.cy())
|
||||
|
||||
# strap_end = vector( self.dummy.width * (self.length + 1), self.via.cy())
|
||||
|
||||
# self.strap = self.add_path(self.strap_layer, (strap_start, strap_end))
|
||||
|
||||
def extend_poly(self):
|
||||
y_offset = 0
|
||||
if self.tx_type == "pmos":
|
||||
|
|
@ -104,8 +84,6 @@ class rom_poly_tap(design):
|
|||
self.add_segment_center("poly", start, vector(self.via.cx() + self.pitch_offset, self.via.cy() + y_offset))
|
||||
self.add_segment_center("poly", start, vector(0, self.via.cy() + y_offset))
|
||||
|
||||
|
||||
|
||||
def place_active_tap(self):
|
||||
gap = self.poly_extend_active - 0.5 * ( self.active_contact.height - self.poly_contact.width )
|
||||
offset = self.active_space - gap
|
||||
|
|
@ -113,17 +91,15 @@ class rom_poly_tap(design):
|
|||
tap_x = self.via.cx() + offset
|
||||
tap_y = self.via.cy() + self.dummy.width * 0.5
|
||||
contact_pos = vector(tap_x, tap_y)
|
||||
|
||||
|
||||
# edge of the next nmos
|
||||
active_edge = self.dummy.width - self.dummy.cell_inst.height - self.poly_extend_active
|
||||
|
||||
|
||||
# edge of the active contact
|
||||
tap_edge = tap_x + 0.5 * self.active_contact.height
|
||||
self.pitch_offset += (self.active_space * 2) - (tap_edge - active_edge) + self.contact_x_offset
|
||||
|
||||
if self.tx_type == "nmos":
|
||||
|
||||
if self.tx_type == "nmos":
|
||||
self.add_via_center(layers=self.active_stack,
|
||||
offset=contact_pos,
|
||||
implant_type="p",
|
||||
|
|
@ -132,6 +108,4 @@ class rom_poly_tap(design):
|
|||
self.add_power_pin(name="gnd",
|
||||
loc=contact_pos,
|
||||
start_layer=self.active_stack[2])
|
||||
self.add_layout_pin_rect_center("active_tap", self.supply_stack[0], contact_pos)
|
||||
|
||||
|
||||
self.add_layout_pin_rect_center("active_tap", self.supply_stack[0], contact_pos)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -13,8 +13,6 @@ from openram.sram_factory import factory
|
|||
from openram.base import vector
|
||||
from openram.tech import layer, drc
|
||||
|
||||
|
||||
|
||||
class rom_precharge_array(design):
|
||||
"""
|
||||
An array of inverters to create the inverted address lines for the rom decoder
|
||||
|
|
@ -38,7 +36,7 @@ class rom_precharge_array(design):
|
|||
else:
|
||||
self.strap_spacing = 0
|
||||
|
||||
|
||||
|
||||
if strap_spacing != 0:
|
||||
self.num_straps = ceil(self.cols / self.strap_spacing)
|
||||
self.array_col_size = self.cols + self.num_straps
|
||||
|
|
@ -54,8 +52,6 @@ class rom_precharge_array(design):
|
|||
self.create_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
|
||||
|
||||
def create_layout(self):
|
||||
self.width = self.cols * self.pmos.width
|
||||
|
|
@ -64,11 +60,10 @@ class rom_precharge_array(design):
|
|||
self.create_layout_pins()
|
||||
self.route_supply()
|
||||
self.connect_taps()
|
||||
|
||||
|
||||
self.add_boundary()
|
||||
self.extend_well()
|
||||
|
||||
|
||||
def add_boundary(self):
|
||||
# self.translate_all(self.well_ll)
|
||||
ur = self.find_highest_coords()
|
||||
|
|
@ -92,7 +87,6 @@ class rom_precharge_array(design):
|
|||
self.add_pin("pre_bl{0}_out".format(col), "OUTPUT")
|
||||
self.add_pin("gate", "INPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
|
||||
|
||||
def create_instances(self):
|
||||
self.array_insts = []
|
||||
|
|
@ -101,13 +95,11 @@ class rom_precharge_array(design):
|
|||
|
||||
self.create_poly_tap(-1)
|
||||
for col in range(self.cols):
|
||||
|
||||
|
||||
if col % self.strap_spacing == 0:
|
||||
self.create_poly_tap(col)
|
||||
self.create_precharge_tx(col)
|
||||
|
||||
|
||||
|
||||
def create_precharge_tx(self, col):
|
||||
name = "pmos_c{0}".format(col)
|
||||
pmos = self.add_inst(name=name, mod=self.pmos)
|
||||
|
|
@ -131,9 +123,9 @@ class rom_precharge_array(design):
|
|||
# columns are bit lines
|
||||
cell_x = 0
|
||||
|
||||
|
||||
|
||||
for col in range(self.cols):
|
||||
|
||||
|
||||
if col % self.strap_spacing == 0:
|
||||
self.tap_insts[strap_num].place(vector(cell_x, cell_y + self.poly_tap.height))
|
||||
strap_num += 1
|
||||
|
|
@ -141,19 +133,11 @@ class rom_precharge_array(design):
|
|||
if self.tap_direction == "col":
|
||||
cell_x += self.poly_tap.pitch_offset
|
||||
|
||||
|
||||
# if col % self.strap_spacing == 0 :
|
||||
# self.tap_insts[strap_num].place(vector(cell_x, cell_y))
|
||||
# self.add_label("debug", "li", vector(cell_x, cell_y))
|
||||
# cell_x += self.poly_tap.width
|
||||
|
||||
self.pmos_insts[col].place(vector(cell_x, cell_y))
|
||||
self.add_label("debug", "li", vector(cell_x, cell_y))
|
||||
cell_x += self.pmos.width
|
||||
print(self.tap_insts)
|
||||
|
||||
self.tap_insts[strap_num].place(vector(cell_x, cell_y + self.poly_tap.height))
|
||||
|
||||
|
||||
def create_layout_pins(self):
|
||||
self.copy_layout_pin(self.tap_insts[0], "poly_tap", "gate")
|
||||
|
|
@ -162,7 +146,6 @@ class rom_precharge_array(design):
|
|||
source_pin = self.pmos_insts[col].get_pin("D")
|
||||
bl = "pre_bl{0}_out".format(col)
|
||||
self.add_layout_pin_rect_center(bl, self.route_layer, source_pin.center())
|
||||
|
||||
|
||||
def route_supply(self):
|
||||
|
||||
|
|
@ -170,9 +153,6 @@ class rom_precharge_array(design):
|
|||
# vdd = [self.pmos_insts[i].get_pin("vdd") for i in range(self.cols)]routeroute_horizon_horizon
|
||||
self.route_horizontal_pins("vdd", insts=self.pmos_insts, layer=self.strap_layer)
|
||||
|
||||
|
||||
|
||||
|
||||
def connect_taps(self):
|
||||
array_pins = [self.tap_insts[i].get_pin("poly_tap") for i in range(len(self.tap_insts))]
|
||||
|
||||
|
|
@ -183,12 +163,8 @@ class rom_precharge_array(design):
|
|||
start = vector(tap_pin.cx(), tap_pin.by())
|
||||
end = vector(start.x, tap.mod.get_pin("poly_tap").cy())
|
||||
self.add_segment_center(layer="poly", start=start, end=end)
|
||||
print(end)
|
||||
offset_start = vector(end.x - self.poly_tap.width + self.poly_extend_active, end.y)
|
||||
offset_end = end + vector(0.5*self.poly_width, 0)
|
||||
print(self.poly_tap.width)
|
||||
print(end)
|
||||
print(offset_start)
|
||||
self.add_segment_center(layer="poly", start=offset_start, end=offset_end)
|
||||
|
||||
def extend_well(self):
|
||||
|
|
@ -198,4 +174,4 @@ class rom_precharge_array(design):
|
|||
well_y = self.get_pin("vdd").cy() - 0.5 * self.nwell_width
|
||||
well_ll = vector(0, well_y)
|
||||
|
||||
self.add_rect("nwell", well_ll, self.width , self.height - well_y)
|
||||
self.add_rect("nwell", well_ll, self.width , self.height - well_y)
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -13,23 +13,18 @@ from openram import OPTS
|
|||
from openram.sram_factory import factory
|
||||
from openram.tech import drc
|
||||
|
||||
|
||||
class rom_precharge_cell(rom_base_cell):
|
||||
|
||||
def __init__(self, name="", route_layer="m1", supply_layer="li"):
|
||||
self.supply_layer = supply_layer
|
||||
super().__init__(name=name, bitline_layer=route_layer)
|
||||
|
||||
|
||||
|
||||
def create_layout(self):
|
||||
super().create_layout()
|
||||
|
||||
self.place_tap()
|
||||
self.extend_well()
|
||||
|
||||
|
||||
|
||||
def add_modules(self):
|
||||
width = pgate.nearest_bin("pmos", drc["minwidth_tx"])
|
||||
self.pmos = factory.create(module_type="ptx",
|
||||
|
|
@ -46,7 +41,6 @@ class rom_precharge_cell(rom_base_cell):
|
|||
)
|
||||
self.connect_inst(["bitline", "gate", "vdd", "vdd"])
|
||||
|
||||
|
||||
def add_pins(self):
|
||||
pin_list = ["vdd", "gate", "bitline"]
|
||||
dir_list = ["POWER", "INPUT", "OUTPUT"]
|
||||
|
|
@ -66,7 +60,6 @@ class rom_precharge_cell(rom_base_cell):
|
|||
#so that the poly taps are far enough apart
|
||||
self.poly_tap_offset = (self.base_width - self.poly_contact.width - self.poly_active_offset) - drc("poly_to_poly")
|
||||
|
||||
|
||||
def extend_well(self):
|
||||
|
||||
well_y = self.get_pin("vdd").cy() - 0.5 * self.nwell_width
|
||||
|
|
@ -75,7 +68,6 @@ class rom_precharge_cell(rom_base_cell):
|
|||
height = self.get_pin("D").cy() + 0.5 * self.nwell_width - well_y
|
||||
self.add_rect("nwell", well_ll, self.width , height)
|
||||
|
||||
|
||||
def place_tap(self):
|
||||
source = self.cell_inst.get_pin("S")
|
||||
|
||||
|
|
@ -91,13 +83,14 @@ class rom_precharge_cell(rom_base_cell):
|
|||
self.add_via_stack_center(offset=pos,
|
||||
from_layer=self.active_stack[2],
|
||||
to_layer=self.supply_layer)
|
||||
|
||||
|
||||
bitline_offset = vector( 2 * (drc("minwidth_{}".format(self.bitline_layer)) + drc("{0}_to_{0}".format(self.bitline_layer))) ,0)
|
||||
|
||||
|
||||
self.add_layout_pin_rect_center("vdd", self.supply_layer, pos - bitline_offset)
|
||||
|
||||
self.add_path(self.supply_layer, [self.get_pin("vdd").center(), pos, self.get_pin("S").center()])
|
||||
|
||||
self.remove_layout_pin("S")
|
||||
|
||||
def place_bitline(self):
|
||||
pass
|
||||
pass
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2022 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -13,7 +13,6 @@ from openram.tech import layer
|
|||
from openram.tech import layer_properties as layer_props
|
||||
from openram import OPTS
|
||||
|
||||
|
||||
class rom_wordline_driver_array(design):
|
||||
"""
|
||||
Creates a Wordline Buffer/Inverter array
|
||||
|
|
@ -82,7 +81,6 @@ class rom_wordline_driver_array(design):
|
|||
height=b.height,
|
||||
add_wells=False)
|
||||
|
||||
|
||||
def route_supplies(self):
|
||||
"""
|
||||
Add a pin for each row of vdd/gnd which
|
||||
|
|
@ -117,7 +115,6 @@ class rom_wordline_driver_array(design):
|
|||
self.wld_inst[row].place(offset=offset)
|
||||
y_offset += self.wld_inst[row].height
|
||||
|
||||
|
||||
self.width = self.wl_driver.width
|
||||
self.height = self.wl_driver.height * self.rows
|
||||
|
||||
|
|
@ -143,7 +140,6 @@ class rom_wordline_driver_array(design):
|
|||
else:
|
||||
wl_offset = out_pin.rc() - vector( 0.5 * route_width, 0)
|
||||
|
||||
|
||||
end = vector(wl_offset.x, \
|
||||
self.get_pin("in_{}".format(row)).cy() + 0.5 * route_width)
|
||||
self.add_segment_center(layer=self.route_layer,
|
||||
|
|
@ -156,7 +152,6 @@ class rom_wordline_driver_array(design):
|
|||
|
||||
self.add_layout_pin_rect_center(text="out_{}".format(row), layer=self.route_layer, offset=end - vector(0, 0.5 * route_width))
|
||||
|
||||
|
||||
def place_taps(self):
|
||||
|
||||
for wl in range(0 , self.rows, self.tap_spacing):
|
||||
|
|
@ -182,7 +177,6 @@ class rom_wordline_driver_array(design):
|
|||
contact_pos = vector( gnd_pin2.cx(), left_edge)
|
||||
self.place_tap(contact_pos, "p")
|
||||
|
||||
|
||||
def place_tap(self, offset, well_type):
|
||||
self.add_via_center(layers=self.active_stack,
|
||||
offset=offset,
|
||||
|
|
@ -196,5 +190,4 @@ class rom_wordline_driver_array(design):
|
|||
pin = "gnd"
|
||||
else:
|
||||
pin = "vdd"
|
||||
self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset)
|
||||
|
||||
self.add_layout_pin_rect_center(text=pin, layer=self.supply_layer, offset=offset)
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -24,10 +24,8 @@ class rom_bank_test(openram_test):
|
|||
debug.info(1, "Testing 1kB rom cell")
|
||||
|
||||
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_1kB", word_size=1)
|
||||
print('wriitng file')
|
||||
a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
|
||||
self.local_check(a)
|
||||
|
||||
|
||||
openram.end_openram()
|
||||
|
||||
|
|
|
|||
|
|
@ -24,10 +24,8 @@ class rom_bank_test(openram_test):
|
|||
debug.info(1, "Testing 2kB rom cell")
|
||||
|
||||
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_2kB", word_size=1)
|
||||
print('wriitng file')
|
||||
a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
|
||||
self.local_check(a)
|
||||
|
||||
|
||||
openram.end_openram()
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -24,10 +24,8 @@ class rom_bank_test(openram_test):
|
|||
debug.info(1, "Testing 4kB rom cell")
|
||||
|
||||
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_4kB", word_size=2)
|
||||
print('wriitng file')
|
||||
a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
|
||||
self.local_check(a)
|
||||
|
||||
|
||||
openram.end_openram()
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -24,10 +24,9 @@ class rom_bank_test(openram_test):
|
|||
debug.info(1, "Testing 8kB rom cell")
|
||||
|
||||
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_8kB", word_size=2)
|
||||
print('wriitng file')
|
||||
a.sp_write(OPTS.openram_temp + 'simulation_file_8kB.sp')
|
||||
self.local_check(a)
|
||||
|
||||
|
||||
|
||||
openram.end_openram()
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
@ -26,7 +26,6 @@ class rom_bank_test(openram_test):
|
|||
a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_64B", word_size=1)
|
||||
|
||||
self.local_check(a)
|
||||
print('wriitng file')
|
||||
a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
|
||||
openram.end_openram()
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2022 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2021 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2022 Regents of the University of California and The Board
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
|
|
|
|||
Loading…
Reference in New Issue