mirror of https://github.com/VLSIDA/OpenRAM.git
implement relationship between delay pinouts
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@ -105,9 +105,29 @@ class control_logic_delay(control_logic_base):
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pinout_list=self.delay_chain_pinout_list)
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def calculate_delay_chain_size(self):
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self.delay_chain_pinout_list = []
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# calculate it... dummy values for now
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self.delay_chain_pinout_list = [2, 12, 13, 15, 29]
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"""
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calculate the pinouts needed for the delay chain based on:
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wl driver delay, bl minus vth delay, precharge duration
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delays 1 & 2 need to be even for polarity
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delays 3 - 5 need to be odd for polarity
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"""
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# TODO: calculate relevant delay constants
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stage_delay = None
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precharge_duration = None
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bitline_vth_delay = None
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delays = []
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# hardcode 2 delay stages as keepout between p_en and wl_en
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delays[1] = 2
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delays[3] = delays[1] + precharge_duration / stage_delay
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# delays[2] can be any even value less than delays[3]
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delays[2] = delays[3] - 1
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# delays[4] hardcoded 2 delays[ ]stages as keepout between p_en and wl_en
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delays[4] = delays[3] + 2
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delays[5] = delays[4] + bitline_vth_delay / stage_delay
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self.delay_chain_pinout_list = delays
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# FIXME: fanout should be used to control delay chain height
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# for now, use default/user-defined fanout constant
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self.delay_chain_fanout_list = self.delay_chain_pinout_list[-1] * [OPTS.delay_chain_fanout_per_stage]
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def setup_signal_busses(self):
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