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OpenRAM
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more top level routing cleanup

This commit is contained in:
Jacob Walker 2023-03-20 17:01:51 -07:00
parent fef9902c45
commit 7805fcb21e
2 changed files with 3 additions and 7 deletions
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1
compiler/modules/rom_address_control_array.py
View File

@ -117,6 +117,5 @@ class rom_address_control_array(design):
self.remove_layout_pin("vdd")
for pin in tmp_pins:
print("copying pin")
self.copy_layout_pin(self, "vdd_edge", "vdd")
self.remove_layout_pin("vdd_edge")

9
compiler/modules/rom_base_array.py
View File

@ -204,11 +204,10 @@ class rom_base_array(bitcell_base_array):
drain_r = self.cell_list[self.row_size][self.column_size - 1].get_pin("D")
gnd_l = drain_l.center() + vector(-0.5 * self.route_width, pitch + via_width + self.route_pitch)
gnd_r = drain_r.center() + vector(0.5 * self.route_width, pitch + via_width + self.route_pitch)
self.add_layout_pin_segment_center(text="gnd", layer=self.bitline_layer, start=gnd_l, end=gnd_r)
self.add_layout_pin_rect_ends(name="gnd", layer=self.bitline_layer, start=gnd_l, end=gnd_r)
if self.tap_direction == "row":
self.route_horizontal_pins("gnd", insts=[self], yside="cy")
self.connect_row_pins(layer=self.wordline_layer, pins=self.gnd_taps, name="gnd")
self.remove_layout_pin("gnd_tap")
@ -217,13 +216,11 @@ class rom_base_array(bitcell_base_array):
active_tap_pins = [self.active_tap_list[i].get_pin("active_tap") for i in range(len(self.active_tap_list))]
self.connect_col_pins(layer=self.supply_stack[0], pins=active_tap_pins, name="gnd_tmp")
for pin in self.get_pins("gnd_tmp"):
bottom = vector(pin.cx(), pin.by())
top = vector(pin.cx(), pin.uy())
bottom = vector(pin.cx(), pin.by() + 0.5 * drc("minwidth_{}".format(self.supply_stack[0])))
top = vector(pin.cx(), pin.uy() - 0.5 * drc("minwidth_{}".format(self.supply_stack[0])))
self.add_layout_pin_rect_ends(layer=self.supply_stack[0], start=bottom, end=top, name="gnd")
self.remove_layout_pin("gnd_tmp")
self.copy_layout_pin(self.precharge_inst, "vdd")
def place_array(self):