mirror of https://github.com/VLSIDA/OpenRAM.git
add skeleton for delay chain sizing
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@ -99,12 +99,16 @@ class control_logic_delay(control_logic_base):
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self.nand2 = factory.create(module_type="pnand2",
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height=dff_height)
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# TODO: is this needed? Should this be used or inferred from the pinout_list?
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debug.check(OPTS.delay_chain_stages % 2,
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"Must use odd number of delay chain stages for inverting delay chain.")
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self.calculate_delay_chain_size()
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self.delay_chain = factory.create(module_type="multi_delay_chain",
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fanout_list=29 * [OPTS.delay_chain_fanout_per_stage], # TODO: generate this programatically
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pinout_list=[2, 12, 13, 15, 29]) # TODO: generate this list programatically
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fanout_list=self.delay_chain_fanout_list,
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pinout_list=self.delay_chain_pinout_list)
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def calculate_delay_chain_size(self):
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self.delay_chain_pinout_list = []
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# calculate it... dummy values for now
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self.delay_chain_pinout_list = [2, 12, 13, 15, 29]
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self.delay_chain_fanout_list = self.delay_chain_pinout_list[-1] * [OPTS.delay_chain_fanout_per_stage]
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def setup_signal_busses(self):
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""" Setup bus names, determine the size of the busses etc """
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