mirror of https://github.com/VLSIDA/OpenRAM.git
rom compiler top level
This commit is contained in:
Jacob Walker
parent
2d5199961d
commit
41f0b9a412
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@ -44,3 +44,6 @@ from .globals import *
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# sram_config should be imported before sram
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from .sram_config import *
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from .sram import *
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from .rom_config import *
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from .rom import *
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@ -72,6 +72,7 @@ from .replica_pbitcell import *
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from .row_cap_array import *
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from .row_cap_bitcell_1port import *
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from .row_cap_bitcell_2port import *
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from .rom_base_bank import *
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from .sense_amp_array import *
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from .sense_amp import *
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from .tri_gate_array import *
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@ -10,7 +10,7 @@
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import math
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from .bitcell_base_array import bitcell_base_array
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from openram.base import vector
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from openram import OPTS
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from openram import OPTS, debug
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from openram.sram_factory import factory
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from openram.tech import drc, layer
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@ -35,6 +35,7 @@ class rom_base_array(bitcell_base_array):
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self.array_col_size = self.column_size
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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# debug.info(1, "ROM array with rows: {0}, cols: {1}".format(self.row_size, self.column_size))
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self.create_netlist()
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self.create_layout()
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@ -148,6 +149,7 @@ class rom_base_array(bitcell_base_array):
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# when col = 0, bl_h is connected to precharge, otherwise connect to previous bl connection
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# when col = col_size - 1 connected column_sizeto gnd otherwise create new bl connection
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# debug.info(1, "Create cell: r{0}, c{1}".format(row, col))
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if row == self.row_size:
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bl_l = self.int_bl_list[col]
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@ -6,10 +6,11 @@
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# All rights reserved.
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#
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import datetime
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from math import ceil, log, sqrt
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from openram.base import vector
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from openram.base import design
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from openram import OPTS, debug
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from openram import OPTS, debug, print_time
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from openram.sram_factory import factory
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from openram.tech import drc, layer, parameter
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@ -21,120 +22,82 @@ class rom_base_bank(design):
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word size is in bytes
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"""
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def __init__(self, strap_spacing=0, data_file=None, name="", word_size=2):
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def __init__(self, name, rom_config):
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super().__init__(name=name)
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self.word_size = word_size * 8
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self.read_binary(word_size=word_size, data_file=data_file, scramble_bits=True, endian="little")
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self.rom_config = rom_config
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rom_config.set_local_config(self)
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self.word_size = self.word_bits
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# self.read_binary(word_size=word_size, data_file=data_file, scramble_bits=True, endian="little")
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# debug.info(1, "Rom data: {}".format(self.data))
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self.num_outputs = self.rows
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self.num_inputs = ceil(log(self.rows, 2))
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self.col_bits = ceil(log(self.words_per_row, 2))
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self.row_bits = self.num_inputs
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# self.data = [[0, 1, 0, 1], [1, 1, 1, 1], [1, 1, 0, 0], [0, 0, 1, 0]]
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self.strap_spacing = strap_spacing
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self.tap_spacing = 8
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self.tap_spacing = self.strap_spacing
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try:
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from openram.tech import power_grid
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self.supply_stack = power_grid
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except ImportError:
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# if no power_grid is specified by tech we use sensible defaults
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# Route a M3/M4 grid
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self.supply_stack = self.m3_stack
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self.interconnect_layer = "m1"
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self.bitline_layer = "m1"
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self.wordline_layer = "m2"
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if "li" in layer:
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self.route_stack = self.m1_stack
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else:
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self.route_stack = self.m2_stack
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self.route_layer = self.route_stack[0]
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self.setup_layout_constants()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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"""
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Reads a hexadecimal file from a given directory to be used as the data written to the ROM
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endian is either "big" or "little"
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word_size is the number of bytes per word
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sets the row and column size based on the size of binary input, tries to keep array as square as possible,
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"""
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def read_binary(self, data_file, word_size=2, endian="big", scramble_bits=False):
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# Read data as hexidecimal text file
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hex_file = open(data_file, 'r')
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hex_data = hex_file.read()
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# Convert from hex into an int
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data_int = int(hex_data, 16)
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# Then from int into a right aligned, zero padded string
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bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
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# Then turn the string into a list of ints
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bin_data = list(bin_string)
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bin_data = [int(x) for x in bin_data]
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# data size in bytes
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data_size = len(bin_data) / 8
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num_words = int(data_size / word_size)
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bytes_per_col = sqrt(num_words)
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self.words_per_row = int(ceil(bytes_per_col /(2*word_size)))
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bits_per_row = self.words_per_row * word_size * 8
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self.cols = bits_per_row
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self.rows = int(num_words / (self.words_per_row))
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chunked_data = []
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for i in range(0, len(bin_data), bits_per_row):
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row_data = bin_data[i:i + bits_per_row]
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if len(row_data) < bits_per_row:
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row_data = [0] * (bits_per_row - len(row_data)) + row_data
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chunked_data.append(row_data)
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# if endian == "big":
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self.data = chunked_data
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if scramble_bits:
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scrambled_chunked = []
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for row_data in chunked_data:
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scambled_data = []
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for bit in range(self.word_size):
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for word in range(self.words_per_row):
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scambled_data.append(row_data[bit + word * self.word_size])
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scrambled_chunked.append(scambled_data)
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self.data = scrambled_chunked
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# self.data.reverse()
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debug.info(1, "Read rom binary: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, num_words, self.cols, self.rows, self.words_per_row))
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def create_netlist(self):
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start_time = datetime.datetime.now()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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if not OPTS.is_unit_test:
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print_time("Submodules", datetime.datetime.now(), start_time)
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def create_layout(self):
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self.create_instances()
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start_time = datetime.datetime.now()
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self.setup_layout_constants()
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self.place_instances()
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if not OPTS.is_unit_test:
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print_time("Placement", datetime.datetime.now(), start_time)
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start_time = datetime.datetime.now()
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self.route_layout()
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if not OPTS.is_unit_test:
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print_time("Routing", datetime.datetime.now(), start_time)
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self.height = self.array_inst.height
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self.width = self.array_inst.width
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self.add_boundary()
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start_time = datetime.datetime.now()
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if not OPTS.is_unit_test:
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# We only enable final verification if we have routed the design
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# Only run this if not a unit test, because unit test will also verify it.
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self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
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print_time("Verification", datetime.datetime.now(), start_time)
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def route_layout(self):
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self.route_decode_outputs()
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self.route_precharge()
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self.route_clock()
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self.route_array_outputs()
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self.place_top_level_pins()
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self.route_supplies()
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self.route_output_buffers()
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self.height = self.array_inst.height
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self.width = self.array_inst.width
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self.add_boundary()
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def setup_layout_constants(self):
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self.route_layer_width = drc["minwidth_{}".format(self.route_stack[0])]
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@ -166,7 +129,7 @@ class rom_base_bank(design):
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# in sky130 the address control buffer is composed of 2 size 2 NAND gates,
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# with a beta of 3, each of these gates has gate capacitance of 2 min sized inverters, therefor a load of 4
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addr_control_buffer_effort = parameter['beta'] + 1
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# a single min sized nmos makes up 1/4 of the input capacitance of a min sized inverter
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bitcell_effort = 0.25
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@ -492,12 +455,72 @@ class rom_base_bank(design):
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pin_num = msb - self.col_bits
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self.copy_layout_pin(self.decode_inst, "A{}".format(pin_num), name)
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def route_supplies(self):
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for inst in self.insts:
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if not inst.mod.name.__contains__("contact"):
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self.copy_layout_pin(inst, "vdd")
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self.copy_layout_pin(inst, "gnd")
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self.copy_layout_pin(inst, "gnd")
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# """
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# Reads a hexadecimal file from a given directory to be used as the data written to the ROM
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# endian is either "big" or "little"
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# word_size is the number of bytes per word
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# sets the row and column size based on the size of binary input, tries to keep array as square as possible,
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# """
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# def read_binary(self, data_file, word_size=2, endian="big", scramble_bits=False):
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# # Read data as hexidecimal text file
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# hex_file = open(data_file, 'r')
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# hex_data = hex_file.read()
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# # Convert from hex into an int
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# data_int = int(hex_data, 16)
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# # Then from int into a right aligned, zero padded string
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# bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
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# # Then turn the string into a list of ints
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# bin_data = list(bin_string)
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# bin_data = [int(x) for x in bin_data]
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# # data size in bytes
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# data_size = len(bin_data) / 8
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# num_words = int(data_size / word_size)
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# bytes_per_col = sqrt(num_words)
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# self.words_per_row = int(ceil(bytes_per_col /(2*word_size)))
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# bits_per_row = self.words_per_row * word_size * 8
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# self.cols = bits_per_row
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# self.rows = int(num_words / (self.words_per_row))
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# chunked_data = []
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# for i in range(0, len(bin_data), bits_per_row):
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# row_data = bin_data[i:i + bits_per_row]
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# if len(row_data) < bits_per_row:
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# row_data = [0] * (bits_per_row - len(row_data)) + row_data
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# chunked_data.append(row_data)
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# # if endian == "big":
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# self.data = chunked_data
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# if scramble_bits:
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# scrambled_chunked = []
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# for row_data in chunked_data:
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# scambled_data = []
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# for bit in range(self.word_size):
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# for word in range(self.words_per_row):
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# scambled_data.append(row_data[bit + word * self.word_size])
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# scrambled_chunked.append(scambled_data)
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# self.data = scrambled_chunked
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# # self.data.reverse()
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# debug.info(1, "Read rom binary: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, num_words, self.cols, self.rows, self.words_per_row))
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@ -53,6 +53,14 @@ class options(optparse.Values):
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num_spare_rows = 0
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num_spare_cols = 0
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###################
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# ROM configuration options
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###################
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rom_endian = "little"
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rom_data = None
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strap_spacing = 8
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scramble_bits = True
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###################
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# Optimization options
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###################
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@ -0,0 +1,160 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import os
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import shutil
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import datetime
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from openram import debug
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from openram import rom_config as config
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from openram import OPTS, print_time
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class rom():
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"""
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This is not a design module, but contains an ROM design instance.
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"""
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def __init__(self, rom_config=None, name=None):
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# Create default configs if custom config isn't provided
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if rom_config is None:
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rom_config = config(rom_data=OPTS.rom_data,
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word_size=OPTS.word_size,
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words_per_row=OPTS.words_per_row,
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rom_endian=OPTS.rom_endian,
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strap_spacing=OPTS.strap_spacing)
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if name is None:
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name = OPTS.output_name
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rom_config.set_local_config(self)
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# reset the static duplicate name checker for unit tests
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# in case we create more than one ROM
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from openram.base import design
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design.name_map=[]
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debug.info(2, "create rom of size {0} with {1} num of words".format(self.word_size,
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self.num_words))
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start_time = datetime.datetime.now()
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self.name = name
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import openram.modules.rom_base_bank as rom
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self.r = rom(name, rom_config)
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self.r.create_netlist()
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if not OPTS.netlist_only:
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self.r.create_layout()
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if not OPTS.is_unit_test:
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print_time("ROM creation", datetime.datetime.now(), start_time)
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def sp_write(self, name, lvs=False, trim=False):
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self.r.sp_write(name, lvs, trim)
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def gds_write(self, name):
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self.r.gds_write(name)
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def verilog_write(self, name):
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self.r.verilog_write(name)
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def extended_config_write(self, name):
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"""Dump config file with all options.
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Include defaults and anything changed by input config."""
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f = open(name, "w")
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var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name)))
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for var_name, var_value in var_dict.items():
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if isinstance(var_value, str):
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f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n")
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else:
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f.write(str(var_name) + " = " + str(var_value)+ "\n")
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f.close()
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def save(self):
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""" Save all the output files while reporting time to do it as well. """
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# Import this at the last minute so that the proper tech file
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# is loaded and the right tools are selected
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from openram import verify
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# Save the spice file
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start_time = datetime.datetime.now()
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spname = OPTS.output_path + self.r.name + ".sp"
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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if not OPTS.netlist_only:
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# Write the layout
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start_time = datetime.datetime.now()
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gdsname = OPTS.output_path + self.r.name + ".gds"
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debug.print_raw("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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if OPTS.check_lvsdrc:
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verify.write_drc_script(cell_name=self.r.name,
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gds_name=os.path.basename(gdsname),
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extract=True,
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Save the LVS file
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start_time = datetime.datetime.now()
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lvsname = OPTS.output_path + self.r.name + ".lvs.sp"
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debug.print_raw("LVS: Writing to {0}".format(lvsname))
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self.sp_write(lvsname, lvs=True)
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if not OPTS.netlist_only and OPTS.check_lvsdrc:
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verify.write_lvs_script(cell_name=self.r.name,
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gds_name=os.path.basename(gdsname),
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sp_name=os.path.basename(lvsname),
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("LVS writing", datetime.datetime.now(), start_time)
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# Save the extracted spice file
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if OPTS.use_pex:
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start_time = datetime.datetime.now()
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# Output the extracted design if requested
|
||||
pexname = OPTS.output_path + self.r.name + ".pex.sp"
|
||||
spname = OPTS.output_path + self.r.name + ".sp"
|
||||
verify.run_pex(self.r.name, gdsname, spname, output=pexname)
|
||||
sp_file = pexname
|
||||
print_time("Extraction", datetime.datetime.now(), start_time)
|
||||
else:
|
||||
# Use generated spice file for characterization
|
||||
sp_file = spname
|
||||
|
||||
# Save a functional simulation file
|
||||
|
||||
# TODO: Characterize the design
|
||||
|
||||
|
||||
# Write the config file
|
||||
start_time = datetime.datetime.now()
|
||||
from shutil import copyfile
|
||||
copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py')
|
||||
debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
|
||||
print_time("Config", datetime.datetime.now(), start_time)
|
||||
|
||||
# TODO: Write the datasheet
|
||||
|
||||
# TODO: Write a verilog model
|
||||
# start_time = datetime.datetime.now()
|
||||
# vname = OPTS.output_path + self.r.name + '.v'
|
||||
# debug.print_raw("Verilog: Writing to {0}".format(vname))
|
||||
# self.verilog_write(vname)
|
||||
# print_time("Verilog", datetime.datetime.now(), start_time)
|
||||
|
||||
# Write out options if specified
|
||||
if OPTS.output_extended_config:
|
||||
start_time = datetime.datetime.now()
|
||||
oname = OPTS.output_path + OPTS.output_name + "_extended.py"
|
||||
debug.print_raw("Extended Config: Writing to {0}".format(oname))
|
||||
self.extended_config_write(oname)
|
||||
print_time("Extended Config", datetime.datetime.now(), start_time)
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
from typing import List
|
||||
from math import log, sqrt, ceil
|
||||
from openram import debug
|
||||
from openram.sram_factory import factory
|
||||
from openram import OPTS
|
||||
|
||||
|
||||
|
||||
class rom_config:
|
||||
""" This is a structure that is used to hold the ROM configuration options. """
|
||||
|
||||
def __init__(self, word_size, rom_data, words_per_row=None, rom_endian="little", scramble_bits=True, strap_spacing=8):
|
||||
self.word_size = word_size
|
||||
self.word_bits = self.word_size * 8
|
||||
self.rom_data = rom_data
|
||||
self.strap_spacing = strap_spacing
|
||||
# TODO: This currently does nothing. It should change the behavior of the chunk funciton.
|
||||
self.endian = rom_endian
|
||||
|
||||
# This should pretty much always be true. If you want to make silicon art you might set to false
|
||||
self.scramble_bits = scramble_bits
|
||||
# This will get over-written when we determine the organization
|
||||
self.words_per_row = words_per_row
|
||||
|
||||
self.compute_sizes()
|
||||
|
||||
def __str__(self):
|
||||
""" override print function output """
|
||||
config_items = ["word_size",
|
||||
"num_words",
|
||||
"words_per_row",
|
||||
"endian",
|
||||
"strap_spacing",
|
||||
"rom_data"]
|
||||
str = ""
|
||||
for item in config_items:
|
||||
val = getattr(self, item)
|
||||
str += "{} : {}\n".format(item, val)
|
||||
return str
|
||||
|
||||
def set_local_config(self, module):
|
||||
""" Copy all of the member variables to the given module for convenience """
|
||||
|
||||
members = [attr for attr in dir(self) if not callable(getattr(self, attr)) and not attr.startswith("__")]
|
||||
|
||||
# Copy all the variables to the local module
|
||||
for member in members:
|
||||
setattr(module, member, getattr(self, member))
|
||||
|
||||
def compute_sizes(self):
|
||||
""" Computes the organization of the memory using data size by trying to make it a rectangle."""
|
||||
|
||||
# Read data as hexidecimal text file
|
||||
hex_file = open(self.rom_data, 'r')
|
||||
hex_data = hex_file.read()
|
||||
|
||||
# Convert from hex into an int
|
||||
data_int = int(hex_data, 16)
|
||||
# Then from int into a right aligned, zero padded string
|
||||
bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
|
||||
|
||||
# Then turn the string into a list of ints
|
||||
bin_data = list(bin_string)
|
||||
raw_data = [int(x) for x in bin_data]
|
||||
|
||||
# data size in bytes
|
||||
data_size = len(raw_data) / 8
|
||||
self.num_words = int(data_size / self.word_size)
|
||||
|
||||
# If this was hard coded, don't dynamically compute it!
|
||||
if not self.words_per_row:
|
||||
|
||||
# Row size if the array was square
|
||||
bytes_per_row = sqrt(self.num_words)
|
||||
|
||||
# Heuristic to value longer wordlines over long bitlines.
|
||||
# The extra factor of 2 in the denominator should make the array less square
|
||||
self.words_per_row = int(ceil(bytes_per_row /(2*self.word_size)))
|
||||
|
||||
self.cols = self.words_per_row * self.word_size * 8
|
||||
self.rows = int(self.num_words / self.words_per_row)
|
||||
|
||||
self.chunk_data(raw_data)
|
||||
|
||||
# Set word_per_row in OPTS
|
||||
OPTS.words_per_row = self.words_per_row
|
||||
debug.info(1, "Read rom data file: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, self.num_words, self.cols, self.rows, self.words_per_row))
|
||||
|
||||
|
||||
def chunk_data(self, raw_data: List[int]):
|
||||
"""
|
||||
Chunks a flat list of bits into rows based on the calculated ROM sizes. Handles scrambling of data
|
||||
"""
|
||||
bits_per_row = self.cols
|
||||
|
||||
chunked_data = []
|
||||
|
||||
for i in range(0, len(raw_data), bits_per_row):
|
||||
row_data = raw_data[i:i + bits_per_row]
|
||||
if len(row_data) < bits_per_row:
|
||||
row_data = [0] * (bits_per_row - len(row_data)) + row_data
|
||||
chunked_data.append(row_data)
|
||||
|
||||
self.data = chunked_data
|
||||
|
||||
if self.scramble_bits:
|
||||
scrambled_chunked = []
|
||||
|
||||
for row_data in chunked_data:
|
||||
scambled_data = []
|
||||
for bit in range(self.word_bits):
|
||||
for word in range(self.words_per_row):
|
||||
scambled_data.append(row_data[bit + word * self.word_bits])
|
||||
scrambled_chunked.append(scambled_data)
|
||||
self.data = scrambled_chunked
|
||||
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2023 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
"""
|
||||
ROM Compiler
|
||||
|
||||
The output files append the given suffixes to the output name:
|
||||
a spice (.sp) file for circuit simulation
|
||||
a GDS2 (.gds) file containing the layout
|
||||
"""
|
||||
|
||||
|
||||
import sys
|
||||
import os
|
||||
import datetime
|
||||
|
||||
# You don't need the next two lines if you're sure that openram package is installed
|
||||
from common import *
|
||||
make_openram_package()
|
||||
import openram
|
||||
|
||||
|
||||
(OPTS, args) = openram.parse_args()
|
||||
|
||||
|
||||
# Check that we are left with a single configuration file as argument.
|
||||
if len(args) != 1:
|
||||
print(openram.USAGE)
|
||||
sys.exit(2)
|
||||
|
||||
# These depend on arguments, so don't load them until now.
|
||||
from openram import debug
|
||||
|
||||
# Parse config file and set up all the options
|
||||
openram.init_openram(config_file=args[0])
|
||||
|
||||
# Only print banner here so it's not in unit tests
|
||||
openram.print_banner()
|
||||
|
||||
# Keep track of running stats
|
||||
start_time = datetime.datetime.now()
|
||||
openram.print_time("Start", start_time)
|
||||
|
||||
|
||||
output_extensions = [ "sp", "v"]
|
||||
# Only output lef/gds if back-end
|
||||
if not OPTS.netlist_only:
|
||||
output_extensions.extend(["gds"])
|
||||
|
||||
output_files = ["{0}{1}.{2}".format(OPTS.output_path,
|
||||
OPTS.output_name, x)
|
||||
for x in output_extensions]
|
||||
debug.print_raw("Output files are: ")
|
||||
for path in output_files:
|
||||
debug.print_raw(path)
|
||||
|
||||
from openram import rom
|
||||
|
||||
r = rom()
|
||||
|
||||
# Output the files for the resulting ROM
|
||||
r.save()
|
||||
|
||||
# Delete temp files etc.
|
||||
openram.end_openram()
|
||||
openram.print_time("End", datetime.datetime.now(), start_time)
|
||||
Loading…
Reference in New Issue