mirror of https://github.com/VLSIDA/OpenRAM.git
add optional guard band to delay chain sizing
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@ -142,21 +142,26 @@ class control_logic_delay(control_logic_base):
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# time for bitline to drop from vdd by threshold voltage once wordline enabled
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bitline_vth_swing = (spice["nom_supply_voltage"] - spice["nom_threshold"]) / spice["nom_supply_voltage"]
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bitline_vth_delay = abs(math.log(1 - bitline_vth_swing)) * spice["wire_unit_r"] * bitline_area * bitline_cap_ff
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print("delays: delay_stage {} precharge {} pen {} wl {} wlen {} vth {}".format(inverter_stage_delay, precharge_delay, pen_signal_delay, wordline_delay, wlen_signal_delay, bitline_vth_delay))
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# print("delays: delay_stage {} precharge {} pen {} wl {} wlen {} vth {}".format(inverter_stage_delay, precharge_delay, pen_signal_delay, wordline_delay, wlen_signal_delay, bitline_vth_delay))
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delays = [None] * 5
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# keepout between p_en rising and wl_en falling
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delays[0] = int((wlen_signal_delay + wordline_delay) / inverter_stage_delay) # could possibly subtract pen_signal_delay?
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delays[0] = (wlen_signal_delay + wordline_delay) / inverter_stage_delay # could possibly subtract pen_signal_delay?
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delays[0] = int(delays[0] * OPTS.delay_control_scaling_factor)
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# round up to nearest even integer
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delays[0] += delays[0] % 2
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delays[2] = delays[0] + (pen_signal_delay + precharge_delay) / inverter_stage_delay
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delays[2] *= OPTS.delay_control_scaling_factor
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# round up to nearest odd integer
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delays[2] = int(1 - (2 * ((1 - delays[2]) // 2)))
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# delays[1] can be any even value less than delays[2]
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delays[1] = delays[2] - 1
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# keepout between p_en falling and wl_en rising
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delays[3] = delays[2] + pen_signal_delay / inverter_stage_delay
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delays[3] *= OPTS.delay_control_scaling_factor
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delays[3] = int(1 - (2 * ((1 - delays[3]) // 2)))
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delays[4] = delays[3] + (wlen_signal_delay + wordline_delay + bitline_vth_delay) / inverter_stage_delay
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delays[4] *= OPTS.delay_control_scaling_factor
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delays[4] = int(1 - (2 * ((1 - delays[4]) // 2)))
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self.delay_chain_pinout_list = delays
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# FIXME: fanout should be used to control delay chain height
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@ -67,9 +67,13 @@ class options(optparse.Values):
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# Approximate percentage of delay compared to bitlines
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rbl_delay_percentage = 0.5
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# Allow manual adjustment of the delay chain over automatic
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auto_delay_chain_sizing = False
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# delay chain is automatically sized in delay based control logic
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# this multiplier can be used to add a guard band to the standard timing
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# lowering it can improve performance but may cause sram to fail
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delay_control_scaling_factor = 1.0
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# stages for delay chain in rbl control logic only
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delay_chain_stages = 9
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# fanout per stage for any control logic
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delay_chain_fanout_per_stage = 4
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accuracy_requirement = 0.75
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