standardize 14* test structure

compiler/tests/14_capped_replica_bitcell_array_dummies_1rw_test.py

@@ -23,6 +23,7 @@ class capped_replica_bitcell_array_dummies_1rw_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 7x5 capped replica array for 1rw cell with dummy row only")
         a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])

compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py

@@ -31,6 +31,7 @@ class capped_replica_bitcell_array_leftrbl_1rw_1r_test(openram_test):
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()

compiler/tests/14_capped_replica_bitcell_array_leftrbl_1rw_test.py

@@ -23,6 +23,7 @@ class capped_replica_bitcell_array_leftrbl_1rw_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 7x5 capped replica array for 1rw cell with left replica column")
         a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])

compiler/tests/14_capped_replica_bitcell_array_norbl_1rw_test.py

@@ -23,6 +23,7 @@ class capped_replica_bitcell_array_norbl_1rw_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 7x5 capped replica array for 1rw cell without replica column or dummy row")
         a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])

compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py

@@ -31,6 +31,7 @@ class capped_replica_bitcell_array_rightrbl_1rw_1r_test(openram_test):
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()

compiler/tests/14_capped_replica_bitcell_array_rightrbl_1rw_test.py

@@ -23,6 +23,7 @@ class capped_replica_bitcell_array_rightrbl_1rw_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 7x5 capped replica array for 1rw cell with right replica column")
         a = factory.create(module_type="capped_replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0])

compiler/tests/14_replica_bitcell_array_dummies_1rw_test.py

@@ -23,8 +23,8 @@ class replica_bitcell_array_dummies_1rw_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
-        factory.reset()
         debug.info(2, "Testing 7x5 replica array for 1rw cell with dummy row only")
         a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0])
         self.local_check(a)

compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py

@@ -31,6 +31,7 @@ class replica_bitcell_array_leftrbl_1rw_1r_test(openram_test):
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()

compiler/tests/14_replica_bitcell_array_leftrbl_1rw_test.py

@@ -23,8 +23,8 @@ class replica_bitcell_array_leftrbl_1rw_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
-        factory.reset()
         debug.info(2, "Testing 7x5 replica array for 1rw cell with left replica column")
         a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], left_rbl=[0])
         self.local_check(a)

compiler/tests/14_replica_bitcell_array_norbl_1rw_test.py

@@ -23,6 +23,7 @@ class replica_bitcell_array_norbl_1rw_test(openram_test):
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
         OPTS.num_w_ports = 0
+        openram.setup_bitcell()
 
         debug.info(2, "Testing 7x5 replica array for 1rw cell without replica column or dummy row")
         a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[0, 0])

compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py

@@ -31,6 +31,7 @@ class replica_bitcell_array_rightrbl_1rw_test(openram_test):
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()

compiler/tests/14_replica_bitcell_array_rightrbl_1rw_test.py

@@ -31,6 +31,7 @@ class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test):
 
         openram.end_openram()
 
+
 # run the test from the command line
 if __name__ == "__main__":
     (OPTS, args) = openram.parse_args()