mirror of https://github.com/VLSIDA/OpenRAM.git
add no rbl support to port address
This commit is contained in:
Sam Crow
parent
ae6d271602
commit
efbb658784
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@ -18,11 +18,12 @@ class port_address(design):
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Create the address port (row decoder and wordline driver)..
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"""
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def __init__(self, cols, rows, port, name=""):
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def __init__(self, cols, rows, port, has_rbl, name=""):
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self.num_cols = cols
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self.num_rows = rows
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self.port = port
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self.has_rbl = has_rbl
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self.addr_size = ceil(log(self.num_rows, 2))
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if name == "":
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@ -41,7 +42,8 @@ class port_address(design):
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self.add_modules()
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self.create_row_decoder()
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self.create_wordline_driver()
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self.create_rbl_driver()
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if self.has_rbl:
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self.create_rbl_driver()
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def create_layout(self):
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if "li" in layer:
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@ -63,7 +65,8 @@ class port_address(design):
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for bit in range(self.num_rows):
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self.add_pin("wl_{0}".format(bit), "OUTPUT")
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self.add_pin("rbl_wl", "OUTPUT")
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if self.has_rbl:
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self.add_pin("rbl_wl", "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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@ -76,12 +79,13 @@ class port_address(design):
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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if layer_props.wordline_driver.vertical_supply:
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self.copy_layout_pin(self.rbl_driver_inst, "vdd")
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else:
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rbl_pos = self.rbl_driver_inst.get_pin("vdd").rc()
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self.add_power_pin("vdd", rbl_pos)
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self.add_path("m4", [rbl_pos, self.wordline_driver_array_inst.get_pins("vdd")[0].rc()])
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if self.has_rbl:
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if layer_props.wordline_driver.vertical_supply:
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self.copy_layout_pin(self.rbl_driver_inst, "vdd")
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else:
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rbl_pos = self.rbl_driver_inst.get_pin("vdd").rc()
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self.add_power_pin("vdd", rbl_pos)
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self.add_path("m4", [rbl_pos, self.wordline_driver_array_inst.get_pins("vdd")[0].rc()])
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self.copy_layout_pin(self.wordline_driver_array_inst, "vdd")
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self.copy_layout_pin(self.wordline_driver_array_inst, "gnd")
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@ -90,11 +94,12 @@ class port_address(design):
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self.copy_layout_pin(self.row_decoder_inst, "gnd")
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# Also connect the B input of the RBL and_dec to vdd
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if OPTS.local_array_size == 0:
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rbl_b_pin = self.rbl_driver_inst.get_pin("B")
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rbl_loc = rbl_b_pin.center() - vector(3 * self.m1_pitch, 0)
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self.add_path(rbl_b_pin.layer, [rbl_b_pin.center(), rbl_loc])
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self.add_power_pin("vdd", rbl_loc, start_layer=rbl_b_pin.layer)
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if self.has_rbl:
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if OPTS.local_array_size == 0:
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rbl_b_pin = self.rbl_driver_inst.get_pin("B")
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rbl_loc = rbl_b_pin.center() - vector(3 * self.m1_pitch, 0)
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self.add_path(rbl_b_pin.layer, [rbl_b_pin.center(), rbl_loc])
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self.add_power_pin("vdd", rbl_loc, start_layer=rbl_b_pin.layer)
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def route_pins(self):
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for row in range(self.addr_size):
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@ -105,7 +110,8 @@ class port_address(design):
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driver_name = "wl_{}".format(row)
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self.copy_layout_pin(self.wordline_driver_array_inst, driver_name)
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self.copy_layout_pin(self.rbl_driver_inst, "Z", "rbl_wl")
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if self.has_rbl:
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self.copy_layout_pin(self.rbl_driver_inst, "Z", "rbl_wl")
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def route_internal(self):
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for row in range(self.num_rows):
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@ -125,24 +131,25 @@ class port_address(design):
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offset=driver_in_pos)
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# Route the RBL from the enable input
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en_pin = self.wordline_driver_array_inst.get_pin("en")
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if self.port == 0:
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en_pos = en_pin.bc()
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else:
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en_pos = en_pin.uc()
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rbl_in_pin = self.rbl_driver_inst.get_pin("A")
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rbl_in_pos = rbl_in_pin.center()
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if self.has_rbl:
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en_pin = self.wordline_driver_array_inst.get_pin("en")
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if self.port == 0:
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en_pos = en_pin.bc()
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else:
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en_pos = en_pin.uc()
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rbl_in_pin = self.rbl_driver_inst.get_pin("A")
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rbl_in_pos = rbl_in_pin.center()
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self.add_via_stack_center(from_layer=rbl_in_pin.layer,
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to_layer=en_pin.layer,
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offset=rbl_in_pos)
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self.add_zjog(layer=en_pin.layer,
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start=rbl_in_pos,
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end=en_pos,
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first_direction="V")
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self.add_layout_pin_rect_center(text="wl_en",
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layer=en_pin.layer,
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offset=rbl_in_pos)
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self.add_via_stack_center(from_layer=rbl_in_pin.layer,
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to_layer=en_pin.layer,
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offset=rbl_in_pos)
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self.add_zjog(layer=en_pin.layer,
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start=rbl_in_pos,
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end=en_pos,
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first_direction="V")
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self.add_layout_pin_rect_center(text="wl_en",
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layer=en_pin.layer,
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offset=rbl_in_pos)
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def add_modules(self):
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@ -164,16 +171,17 @@ class port_address(design):
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# to compensate for the local array inverters
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b = factory.create(module_type=OPTS.bitcell)
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if local_array_size > 0:
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# The local wordline driver will change the polarity
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self.rbl_driver = factory.create(module_type="inv_dec",
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size=driver_size,
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height=b.height)
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else:
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# There is no local wordline driver
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self.rbl_driver = factory.create(module_type="and2_dec",
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size=driver_size,
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height=b.height)
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if self.has_rbl:
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if local_array_size > 0:
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# The local wordline driver will change the polarity
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self.rbl_driver = factory.create(module_type="inv_dec",
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size=driver_size,
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height=b.height)
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else:
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# There is no local wordline driver
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self.rbl_driver = factory.create(module_type="and2_dec",
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size=driver_size,
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height=b.height)
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def create_row_decoder(self):
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""" Create the hierarchical row decoder """
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@ -231,16 +239,17 @@ class port_address(design):
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wordline_driver_array_offset = vector(self.row_decoder_inst.rx(), 0)
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self.wordline_driver_array_inst.place(wordline_driver_array_offset)
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# This m4_pitch corresponds to the offset space for jog routing in the
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# wordline_driver_array
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rbl_driver_offset = wordline_driver_array_offset + vector(2 * self.m4_pitch, 0)
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if self.has_rbl:
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# This m4_pitch corresponds to the offset space for jog routing in the
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# wordline_driver_array
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rbl_driver_offset = wordline_driver_array_offset + vector(2 * self.m4_pitch, 0)
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if self.port == 0:
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self.rbl_driver_inst.place(rbl_driver_offset, "MX")
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else:
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rbl_driver_offset += vector(0,
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self.wordline_driver_array.height)
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self.rbl_driver_inst.place(rbl_driver_offset)
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if self.port == 0:
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self.rbl_driver_inst.place(rbl_driver_offset, "MX")
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else:
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rbl_driver_offset += vector(0,
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self.wordline_driver_array.height)
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self.rbl_driver_inst.place(rbl_driver_offset)
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# Pass this up
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self.predecoder_height = self.row_decoder.predecoder_height
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