mirror of https://github.com/VLSIDA/OpenRAM.git
more code cleaning
This commit is contained in:
Jacob Walker
parent
90cf382a43
commit
92251fe61e
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@ -56,10 +56,8 @@ class rom_address_control_array(design):
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def create_modules(self):
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self.addr_control = factory.create(module_type="rom_address_control_buf", size=self.inv_height)
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# For layout constants
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# self.poly_tap = factory.create(module_type="rom_poly_tap", strap_length=0)
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def add_pins(self):
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for col in range(self.cols):
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@ -41,16 +41,13 @@ class rom_address_control_buf(design):
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self.height = self.inv.width + 2 * self.nand.width
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self.setup_layout_constants()
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self.place_instances()
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# self.place_vias()
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self.route_gates()
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self.route_sources()
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self.add_boundary()
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def create_modules(self):
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# self.inv1_mod = factory.create(module_type="pinv", module_name="inv_array_end_mod", height=self.inv_size, add_wells=False)
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self.inv = factory.create(module_type="pinv_dec", module_name="inv_array_mod", add_wells=False, size=self.size)
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# self.end_inv = factory.create(module_type="pinv", module_name="inv_array_end_mod", size=self.size, add_wells=True)
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self.nand = factory.create(module_type="nand2_dec", height=self.inv.height)
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# For layout constants
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self.cell = factory.create(module_type="rom_base_cell")
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@ -101,7 +98,6 @@ class rom_address_control_buf(design):
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def route_gates(self):
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clk1_pin = self.addr_nand.get_pin("A")
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clk2_pin = self.addr_bar_nand.get_pin("A")
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# self.add_label("HERE I AM", "poly", clk_pins.cl())
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Abar_out = self.addr_bar_nand.get_pin("Z")
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A_out = self.addr_nand.get_pin("Z")
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@ -115,21 +115,17 @@ class rom_base_array(bitcell_base_array):
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# list of current bitline interconnect nets,
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# starts as the same as the bitline list and is updated when new insts of cells are added
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self.int_bl_list = self.bitline_names[0].copy()
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#When rotated correctly rows are word lines
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for row in range(self.row_size + 1):
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row_list = []
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# for each new strap placed, offset the column index refrenced to get correct bit in the data array
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# cols are bit lines
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for col in range(self.column_size):
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if col % self.strap_spacing == 0:
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self.create_poly_tap(row, col)
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new_inst = self.create_cell(row, col)
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self.cell_inst[row, col] = new_inst
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row_list.append(new_inst)
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name = "tap_r{0}_c{1}".format(row, self.array_col_size)
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@ -206,8 +202,8 @@ class rom_base_array(bitcell_base_array):
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def place_array(self):
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self.cell_pos = {}
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self.strap_pos = {}
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# rows are wordlines
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pitch_offset = 0
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for row in range(self.row_size + 1):
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if row % self.tap_spacing == 0 and self.pitch_match and row != self.row_size:
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@ -228,7 +224,6 @@ class rom_base_array(bitcell_base_array):
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self.cell_pos[row, col] = vector(cell_x, cell_y)
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self.cell_inst[row, col].place(self.cell_pos[row, col])
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cell_x += self.zero_cell.width
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# self.add_label("debug", "li", self.cell_pos[row, col])
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self.strap_pos[row, self.column_size] = vector(cell_x, cell_y)
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self.tap_inst[row, self.column_size].place(self.strap_pos[row, self.column_size])
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@ -338,24 +333,6 @@ class rom_base_array(bitcell_base_array):
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array_pins = [self.tap_list[i].get_pin("poly_tap") for i in range(len(self.tap_list))]
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self.connect_row_pins(layer=self.wordline_layer, pins=array_pins, name=None, round=False)
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# self.connect_row_pins(layer="poly", pins=array_pins, name=None, round=False)
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if self.tap_direction == "col":
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self.route_vertical_pins("active_tap", insts=self.tap_list, layer=self.supply_stack[0], full_width=False)
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def get_next_cell_in_bl(self, row_start, col):
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for row in range(row_start + 1, self.row_size):
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if self.data[row][col] == 1:
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return row
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return -1
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def get_current_bl_interconnect(self, col):
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"""Get interconnect net for bitline(col) currently being connected """
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return "bli_{0}_{1}".format(self.current_row, col)
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def create_next_bl_interconnect(self, row, col):
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"""create a new net name for a bitline interconnect"""
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self.current_row = row
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return "bli_{0}_{1}".format(row, col)
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self.route_vertical_pins("active_tap", insts=self.tap_list, layer=self.supply_stack[0], full_width=False)
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@ -11,7 +11,7 @@ from openram.base import vector
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from openram.base import design
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from openram import OPTS, debug
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from openram.sram_factory import factory
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from openram.tech import drc, layer
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from openram.tech import drc, layer, parameter
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class rom_base_bank(design):
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@ -165,7 +165,9 @@ class rom_base_bank(design):
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# TODO: provide technology-specific calculation of these parameters
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# in sky130 the address control buffer is composed of 2 size 2 NAND gates,
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# with a beta of 3, each of these gates has gate capacitance of 2 min sized inverters, therefor a load of 4
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addr_control_buffer_effort = 4
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addr_control_buffer_effort = parameter['beta'] + 1
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# a single min sized nmos makes up 1/4 of the input capacitance of a min sized inverter
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bitcell_effort = 0.25
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@ -23,13 +23,10 @@ class rom_base_cell(design):
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self.create_netlist()
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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def create_layout(self):
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self.create_tx()
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@ -41,34 +38,10 @@ class rom_base_cell(design):
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if self.bit_value == 0:
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self.short_gate()
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# Calculates offsets of cell width and height so that tiling of cells does not violate any drc rules
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def setup_drc_offsets(self):
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self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active)
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#nmos contact to gate distance
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self.contact_to_gate = 0.5 * (self.nmos.width - 2 * self.nmos.contact_width - self.nmos.poly_width - 2 * self.active_enclose_contact)
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#height offset to account for active-to-active spacing between adjacent bitlines
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self.poly_extend_active_spacing = abs( 2 * self.nmos.poly_extend_active - drc("active_to_active") )
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#contact to contact distance, minimum cell width before drc offsets
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self.base_width = self.nmos.width - 2 * self.active_enclose_contact - self.nmos.contact_width
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#width offset to account for active-to-active spacing between cells on the same bitline
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#this is calculated as a negative value
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self.cell_diffusion_offset = ((self.base_width - 2 * self.active_enclose_contact - self.nmos.contact_width) - drc("active_to_active")) * 0.5
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# width offset to account for poly-active spacing between base and dummy cells on the same bitline
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self.poly_active_offset = 0.5 * (self.base_width - 2 * self.cell_diffusion_offset - (self.poly_width + 2 * self.active_enclose_contact + self.nmos.contact_width)) - self.poly_to_active
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#so that the poly taps are far enough apart
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self.poly_tap_offset = (self.base_width - self.cell_diffusion_offset - self.poly_contact.width - self.poly_active_offset) - drc("poly_to_poly")
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def add_boundary(self):
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@ -76,8 +49,7 @@ class rom_base_cell(design):
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#cell width with offsets applied, height becomes width when the cells are rotated
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width = self.cell_inst.height + 2 * self.poly_extend_active
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# cell height with offsets applied, width becomes height when the cells are rotated, if the offsets are positive (greater than 0) they are not applied
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# height = self.base_width - min(self.cell_diffusion_offset, 0) - min(self.poly_active_offset, 0) - min(self.poly_tap_offset, 0)
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# make the cells square so the pitch of wordlines will match bitlines
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@ -30,19 +30,12 @@ class rom_column_mux(pgate):
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self.output_layer= output_layer
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super().__init__(name)
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def get_bl_names(self):
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return "bl"
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def create_netlist(self):
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self.add_pins()
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self.add_ptx()
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def create_layout(self):
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self.pin_layer = self.input_layer
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self.pin_pitch = getattr(self, "{}_pitch".format(self.pin_layer))
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self.pin_width = getattr(self, "{}_width".format(self.pin_layer))
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@ -54,7 +47,6 @@ class rom_column_mux(pgate):
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else:
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self.col_mux_stack = self.m1_stack
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self.place_ptx()
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self.width = self.bitcell.width
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@ -108,14 +100,6 @@ class rom_column_mux(pgate):
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+ vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0)
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self.nmos_lower.place(nmos_lower_position)
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# # This aligns it directly above the other tx with gates abutting
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# nmos_upper_position = nmos_lower_position \
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# + vector(0, self.nmos.active_height + max(self.active_space, self.poly_space))
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# self.nmos_upper.place(nmos_upper_position)
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# if cell_props.pgate.add_implants:
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# self.extend_implants()
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def connect_poly(self):
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""" Connect the poly gate of the two pass transistors """
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@ -137,7 +121,6 @@ class rom_column_mux(pgate):
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""" Connect the bitlines to the mux transistors """
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bl_pin = self.get_pin("bl")
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# br_pin = self.get_pin("br")
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bl_out_pin = self.get_pin("bl_out")
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nmos_lower_s_pin = self.nmos_lower.get_pin("S")
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@ -166,31 +149,11 @@ class rom_column_mux(pgate):
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self.add_path(self.output_layer,
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[bl_out_pin.uc(), mid1, mid2, nmos_lower_d_pin.center()])
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def extend_implants(self):
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"""
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Add top-to-bottom implants for adjacency issues in s8.
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"""
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# Route to the bottom
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ll = (self.nmos_lower.ll() - vector(2 * [self.implant_enclose_active])).scale(1, 0)
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# Don't route to the top
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ur = self.nmos_upper.ur() + vector(self.implant_enclose_active, 0)
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self.add_rect("nimplant",
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ll,
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ur.x - ll.x,
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ur.y - ll.y)
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def add_pn_wells(self):
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"""
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Add a well and implant over the whole cell. Also, add the
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pwell contact (if it exists)
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"""
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# if(cell_props.use_strap == True and OPTS.num_ports == 1):
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# strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version)
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# rbc_width = self.bitcell.width + strap.width
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# else:
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# rbc_width = self.bitcell.width
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# Add it to the right, aligned in between the two tx
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active_pos = vector(self.bitcell.width,
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self.nmos_lower.uy() + self.active_contact.height + self.active_space)
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@ -30,7 +30,6 @@ class rom_column_mux_array(design):
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self.words_per_row = int(self.columns / self.word_size)
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self.input_layer = input_layer
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self.tap_spacing = tap_spacing
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# self.sel_layer = layer_props.column_mux_array.select_layer
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self.sel_layer = sel_layer
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self.sel_pitch = getattr(self, self.sel_layer + "_pitch")
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@ -107,12 +106,6 @@ class rom_column_mux_array(design):
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# For every column, add a pass gate
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for col_num, xoffset in enumerate(self.offsets[0:self.columns]):
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# if self.cell.mirror.y and (col_num + self.column_offset) % 2:
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# mirror = "MY"
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# xoffset = xoffset + self.mux.width
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# else:
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# mirror = ""
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offset = vector(xoffset, self.route_height)
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self.mux_inst[col_num].place(offset=offset)
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@ -206,11 +199,6 @@ class rom_column_mux_array(design):
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offset=bl_out_offset_begin,
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directions=self.via_directions)
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def add_taps(self):
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pass
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def graph_exclude_columns(self, column_include_num):
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"""
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Excludes all columns muxes unrelated to the target bit being simulated.
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@ -14,9 +14,10 @@ from openram.tech import drc
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class rom_decoder(design):
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def __init__(self, num_outputs, fanout, strap_spacing, name="", route_layer="m1", output_layer="m1", invert_outputs=False):
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# word lines/ rows / inputs in the base array become the address lines / cols / inputs in the decoder
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# bit lines / cols / outputs in the base array become the word lines / rows / outputs in the decoder
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# array gets rotated 90deg so that rows/cols switch
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# word lines in the base array become the address lines/cols in the decoder
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# bit lines in the base array become the word lines/rows in the decoder
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# array gets rotated 90deg so rows/cols switch
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self.strap_spacing=strap_spacing
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self.num_outputs = num_outputs
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self.num_inputs = ceil(log(num_outputs, 2))
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@ -204,8 +205,6 @@ class rom_decoder(design):
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self.copy_layout_pin(self.wordline_buf_inst, "out_{}".format(j), "wl_{}".format(j))
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offset = self.wordline_buf_inst.get_pin("out_{}".format(j)).center()
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# self.add_via_stack_center(offset, self.output_layer, self.wordline_buf.route_layer)
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array_pins = [self.array_inst.get_pin("bl_0_{}".format(bl)) for bl in range(self.num_outputs)]
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driver_pins = [self.wordline_buf_inst.get_pin("in_{}".format(bl)) for bl in range(self.num_outputs)]
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@ -233,8 +232,6 @@ class rom_decoder(design):
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self.add_path(self.inv_route_layer, [addr_bar_out_pin.center(), addr_bar_middle, addr_bar_pin.center()])
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self.copy_layout_pin(self.buf_inst, "A{}_in".format(i), "A{}".format(i))
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# self.add_segment_center(self.inv_route_layer, addr_bar_middle + vector(0, self.inv_route_width * 0.5), addr_bar_out_pin.center() + vector(0, self.inv_route_width * 0.5), self.inv_route_width)
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def route_supplies(self):
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self.copy_layout_pin(self.array_inst, "vdd")
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@ -38,8 +38,6 @@ class rom_poly_tap(design):
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def add_boundary(self):
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contact_width = self.poly_contact.width
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# offset = self.active_space - (contact_width - self.active_enclose_contact - self.active_extend_contact)
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self.height = self.dummy.height
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self.width = contact_width + self.pitch_offset
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@ -82,7 +80,6 @@ class rom_poly_tap(design):
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def place_active_tap(self):
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gap = self.poly_extend_active - 0.5 * ( self.active_contact.height - self.poly_contact.width )
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offset = self.active_space - gap
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# tap_x = self.via.cx() + self.contact_width + self.active_enclose_contact + self.poly_enclose_contact
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tap_x = self.via.cx() + offset
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tap_y = self.via.cy() + self.dummy.width * 0.5
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contact_pos = vector(tap_x, tap_y)
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@ -149,8 +149,6 @@ class rom_precharge_array(design):
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def route_supply(self):
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# self.vdd = self.add_layout_pin_segment_center("vdd", self.supply_layer, start, end)
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# vdd = [self.pmos_insts[i].get_pin("vdd") for i in range(self.cols)]routeroute_horizon_horizon
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self.route_horizontal_pins("vdd", insts=self.pmos_insts, layer=self.strap_layer)
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def connect_taps(self):
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@ -51,20 +51,10 @@ class rom_precharge_cell(rom_base_cell):
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self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active)
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#contact to contact distance, minimum cell width before drc offsets
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self.base_width = self.pmos.width - 2 * self.active_enclose_contact - self.pmos.contact_width
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# width offset to account for poly-active spacing between base and dummy cells on the same bitline
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self.poly_active_offset = 0.5 * (self.base_width - (self.poly_width + 2 * self.active_enclose_contact + self.pmos.contact_width)) - self.poly_to_active
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#so that the poly taps are far enough apart
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self.poly_tap_offset = (self.base_width - self.poly_contact.width - self.poly_active_offset) - drc("poly_to_poly")
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def extend_well(self):
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well_y = self.get_pin("vdd").cy() - 0.5 * self.nwell_width
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well_ll = vector(0, well_y)
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# height = self.active_width + 2 * self.well_enclose_active
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height = self.get_pin("D").cy() + 0.5 * self.nwell_width - well_y
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self.add_rect("nwell", well_ll, self.width , height)
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@ -88,8 +88,6 @@ class rom_wordline_driver_array(design):
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"""
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||||
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||||
if layer_props.wordline_driver.vertical_supply:
|
||||
# self.route_vertical_pins("vdd", self.wld_inst)
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||||
# self.route_vertical_pins("gnd", self.wld_inst)
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||||
self.route_vertical_pins("vdd", [self], layer=self.supply_layer)
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||||
self.route_vertical_pins("gnd", [self], layer=self.supply_layer)
|
||||
else:
|
||||
|
|
|
|||
Loading…
Reference in New Issue