mirror of https://github.com/VLSIDA/OpenRAM.git
reflect the changes to sram.py from dev
This commit is contained in:
Bugra Onal
parent
49efff3384
commit
6841de4a50
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@ -35,34 +35,23 @@ class sram():
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if name is None:
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name = OPTS.output_name
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self.name = name
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self.config = sram_config
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sram_config.setup_multiport_constants()
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sram_config.set_local_config(self)
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self.sp_name = OPTS.output_path + self.name + ".sp"
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self.lvs_name = OPTS.output_path + self.name + ".lvs.sp"
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self.pex_name = OPTS.output_path + self.name + ".pex.sp"
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self.gds_name = OPTS.output_path + self.name + ".gds"
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self.lef_name = OPTS.output_path + self.name + ".lef"
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self.v_name = OPTS.output_path + self.name + ".v"
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# reset the static duplicate name checker for unit tests
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# in case we create more than one SRAM
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from openram.base import design
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design.name_map=[]
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self.create()
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def create(self):
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debug.info(2, "create sram of size {0} with {1} num of words {2} banks".format(self.word_size,
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self.num_words,
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self.num_banks))
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start_time = datetime.datetime.now()
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self.name = name
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from openram.modules.sram_1bank import sram_1bank as sram
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self.s = sram(self.name, self.config)
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self.s = sram(name, sram_config)
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self.s.create_netlist()
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if not OPTS.netlist_only:
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@ -118,12 +107,13 @@ class sram():
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# Save the spice file
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start_time = datetime.datetime.now()
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debug.print_raw("SP: Writing to {0}".format(self.sp_name))
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self.sp_write(self.sp_name)
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spname = OPTS.output_path + self.s.name + ".sp"
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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# Save a functional simulation file with default period
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functional(self.s,
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os.path.basename(self.sp_name),
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os.path.basename(spname),
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cycles=200,
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output_path=OPTS.output_path)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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@ -131,7 +121,7 @@ class sram():
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# Save stimulus and measurement file
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start_time = datetime.datetime.now()
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debug.print_raw("DELAY: Writing stimulus...")
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d = delay(self.s, self.get_sp_name(), ("TT", 5, 25), output_path=OPTS.output_path)
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d = delay(self.s, spname, ("TT", 5, 25), output_path=OPTS.output_path)
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if (self.s.num_spare_rows == 0):
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probe_address = "1" * self.s.addr_size
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else:
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@ -150,11 +140,12 @@ class sram():
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if not OPTS.netlist_only:
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# Write the layout
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start_time = datetime.datetime.now()
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debug.print_raw("GDS: Writing to {0}".format(self.gds_name))
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self.gds_write(self.gds_name)
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gdsname = OPTS.output_path + self.s.name + ".gds"
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debug.print_raw("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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if OPTS.check_lvsdrc:
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verify.write_drc_script(cell_name=self.s.name,
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gds_name=os.path.basename(self.gds_name),
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gds_name=os.path.basename(gdsname),
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extract=True,
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final_verification=True,
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output_path=OPTS.output_path)
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@ -162,18 +153,20 @@ class sram():
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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debug.print_raw("LEF: Writing to {0}".format(self.lef_name))
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self.lef_write(self.lef_name)
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lefname = OPTS.output_path + self.s.name + ".lef"
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debug.print_raw("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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# Save the LVS file
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start_time = datetime.datetime.now()
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debug.print_raw("LVS: Writing to {0}".format(self.lvs_name))
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self.sp_write(self.lvs_name, lvs=True)
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lvsname = OPTS.output_path + self.s.name + ".lvs.sp"
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debug.print_raw("LVS: Writing to {0}".format(lvsname))
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self.sp_write(lvsname, lvs=True)
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if not OPTS.netlist_only and OPTS.check_lvsdrc:
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verify.write_lvs_script(cell_name=self.s.name,
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gds_name=os.path.basename(self.gds_name),
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sp_name=os.path.basename(self.lvs_name),
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gds_name=os.path.basename(gdsname),
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sp_name=os.path.basename(lvsname),
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final_verification=True,
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output_path=OPTS.output_path)
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print_time("LVS writing", datetime.datetime.now(), start_time)
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@ -182,14 +175,20 @@ class sram():
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if OPTS.use_pex:
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start_time = datetime.datetime.now()
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# Output the extracted design if requested
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verify.run_pex(self.s.name, self.gds_name, self.sp_name, output=self.pex_name)
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pexname = OPTS.output_path + self.s.name + ".pex.sp"
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spname = OPTS.output_path + self.s.name + ".sp"
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verify.run_pex(self.s.name, gdsname, spname, output=pexname)
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sp_file = pexname
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print_time("Extraction", datetime.datetime.now(), start_time)
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else:
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# Use generated spice file for characterization
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sp_file = spname
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# Characterize the design
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start_time = datetime.datetime.now()
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from openram.characterizer import lib
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debug.print_raw("LIB: Characterizing... ")
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=self.get_sp_name())
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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print_time("Characterization", datetime.datetime.now(), start_time)
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# Write the config file
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