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fix bug in right rbl dual port replica array test

This commit is contained in:
Sam Crow 2023-04-07 11:30:15 -07:00
parent 5b701d828e
commit dff94a032e
1 changed files with 4 additions and 4 deletions
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8
compiler/tests/14_replica_bitcell_array_rightrbl_1rw_1r_test.py
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@ -14,19 +14,19 @@ from openram.sram_factory import factory
from openram import OPTS
class replica_bitcell_array_rightrbl_1rw_test(openram_test):
class replica_bitcell_array_rightrbl_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 7x5 replica array for 1rw cell with right replica column")
a = factory.create(module_type="replica_bitcell_array", cols=7, rows=5, rbl=[1, 0], right_rbl=[0])
debug.info(2, "Testing 4x4 replica array for 1rw1r cell with right replica column")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
openram.end_openram()