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apply 14* standard to 15_local tests

This commit is contained in:
Sam Crow 2023-04-03 10:11:49 -07:00
parent 9181f6a218
commit 83b25138d0
4 changed files with 2 additions and 110 deletions
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59
compiler/tests/15_local_bitcell_array_1rw_1r_test.py
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@ -1,59 +0,0 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
# @unittest.skip("SKIPPING 05_local_bitcell_array_test")
class local_bitcell_array_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local array for 1rw1r cell without replica columns or dummy rows")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0])
self.local_check(a)
debug.info(2, "Testing 4x4 local array for 1rw1r cell with dummy rows only")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1])
self.local_check(a)
debug.info(2, "Testing 4x4 local array for 1rw1r cell with left replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0])
self.local_check(a)
debug.info(2, "Testing 4x4 local array for 1rw1r cell with right replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], right_rbl=[1])
self.local_check(a)
debug.info(2, "Testing 4x4 local array for 1rw1r cell with both replica columns")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 1], left_rbl=[0], right_rbl=[1])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())

51
compiler/tests/15_local_bitcell_array_1rw_test.py
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@ -1,51 +0,0 @@
#!/usr/bin/env python3
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2023 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import sys, os
import unittest
from testutils import *
import openram
from openram import debug
from openram.sram_factory import factory
from openram import OPTS
# @unittest.skip("SKIPPING 05_local_bitcell_array_test")
class local_bitcell_array_1rw_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
openram.init_openram(config_file, is_unit_test=True)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
openram.setup_bitcell()
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column or dummy row")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[0, 0])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica column but with dummy row")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0])
self.local_check(a)
debug.info(2, "Testing 4x4 local bitcell array for 6t_cell with replica column")
a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0], left_rbl=[0])
self.local_check(a)
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main(testRunner=debugTestRunner())

1
compiler/tests/15_local_bitcell_array_leftrbl_1rw_1r_test.py
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@ -31,6 +31,7 @@ class local_bitcell_array_leftrbl_1rw_1r_test(openram_test):
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()

1
compiler/tests/15_local_bitcell_array_rightrbl_1rw_1r_test.py
View File

@ -31,6 +31,7 @@ class local_bitcell_array_rightrbl_1rw_1r_test(openram_test):
openram.end_openram()
# run the test from the command line
if __name__ == "__main__":
(OPTS, args) = openram.parse_args()