luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,545 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

865 Commits

Author SHA1 Message Date
mrg a862cf3cb2 Test more single level col mux configs 2020-06-15 10:17:54 -07:00
mrg 6c04166876 Update port data wmask tests 2020-06-15 06:05:05 -07:00
mrg 9930b5f3f6 Do not run tapless unit tests 2020-06-14 14:18:25 -07:00
mrg 33a32101c9 DRC and LVS fixes for pinv_dec 2020-06-12 15:23:51 -07:00
mrg dff28a9997 Merge branch 'tech_migration' into dev 2020-06-10 17:09:05 -07:00
mrg fdf92d0da1 Rename test 14 2020-06-10 16:41:26 -07:00
mrg 469cd260b9 Change bitcell array name to match 2020-06-10 14:54:20 -07:00
mrg f2c45a230e Add new replica column test. Add more skip tests. 2020-06-10 11:00:00 -07:00
mrg 10be2d08b5 Full path to skip tests file 2020-06-10 10:23:05 -07:00
mrg c119e60e79 Add more s8 skip tests 2020-06-10 10:14:52 -07:00
mrg d4fc88124a Rename dff_buf test 2020-06-09 17:18:19 -07:00
mrg 14782914b3 Remove vertical pand gates 2020-06-09 16:40:59 -07:00
mrg c6b875146d Use local skip file 2020-06-09 16:33:59 -07:00
mrg fd49d3ed6a Add tech specific skip tests for making new techs. 2020-06-09 16:09:15 -07:00
mrg 580b0601b5 Unskip 20_psram_1bank_4mux_1rw_1r_test 2020-06-09 16:04:39 -07:00
mrg a28e747a02 Fix precharge offset. Move well rules to design class. 2020-06-09 15:28:50 -07:00
Aditi Sinha c39c0efd39 Updated spare col tests 2020-06-08 16:38:18 +00:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
mrg 4fef632dce Fix syntax error 2020-06-05 12:13:41 -07:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
mrg 2e7f9395f2 Rename 05 test to 14 2020-06-05 09:57:16 -07:00
mrg 68ffb94d2e Rename 05 test to 14 2020-06-05 09:55:57 -07:00
mrg fb3acae908 PEP8 format testutils. 2020-06-05 09:44:30 -07:00
mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working. 2020-06-04 16:01:32 -07:00
mrg 77c95b28da Rename precharge test 2020-06-03 16:39:46 -07:00
mrg 4183638f03 Align precharge bitlines with col mux 2020-06-03 16:05:57 -07:00
mrg 4bc1e9a026 Fix the bitline spacing in the column mux to a constant. 2020-06-03 15:47:03 -07:00
mrg e93f3f1d2e Add 1rw_1r tests 2020-06-03 14:30:15 -07:00
mrg b78166c044 Merge branch 'dev' into tech_migration 2020-06-03 14:08:22 -07:00
Joey Kunzler 6430aad857 Merge branch 'dev' into s8_update 2020-06-03 11:53:33 -07:00
mrg 38f5e8b865 Add col mux tests for multiport 2020-06-03 10:01:02 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
mrg 34209dac3d A port option for correct mirroring in port_data. 2020-06-02 16:50:07 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg fce8e878b9 Add port to col mux and simplify route with computation to fix mirror bug. 2020-06-02 13:57:41 -07:00
mrg b3b03d4d39 Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 218a553ac5 fix for replica column mirroring over y 2020-05-28 20:31:21 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg 617bf302d1 Add option to remove wells. Save area in pgates with redundant wells. 2020-05-13 14:46:42 -07:00
mrg c96a6d0b9d Add no well option. Add stack gates vertical option. 2020-05-11 16:22:08 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Aditi Sinha e30938fb66 Spare columns working at bank level 2020-05-03 15:23:30 +00:00
Aditi Sinha 49918b0716 New lib syntax for golden results 2020-05-02 09:44:56 +00:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
Matt Guthaus fb17abb16c Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-04-22 10:40:27 -07:00
Matt Guthaus 14f440df73 Update golden results with new lib syntax 2020-04-22 10:40:04 -07:00
Joey Kunzler 60ba2c1aa5 updated pbitcell test names 2020-04-21 17:20:29 -07:00
Joey Kunzler ee1de9ac8c Merge branch 's8_update' of github.com:VLSIDA/PrivateRAM into s8_update 2020-04-20 22:14:09 -07:00
mrg 8c177f9947 Split col mux test 2020-04-20 15:03:32 -07:00
mrg 69d0e5e372 Split port data test into single and multi-port. 2020-04-20 14:26:44 -07:00
mrg cbb67ad483 Update to run LVS when no DRC errors too. 2020-04-17 13:57:52 -07:00
Joey Kunzler fbc6dfdaac split pbitcell tests 2020-04-17 12:26:18 -07:00
mrg f1925420cf Only allow DRC fail with LVS pass if using Magic. 2020-04-17 10:30:26 -07:00
mrg 75fce9894c Allow LVS to run even if DRC fails. 2020-04-17 09:35:07 -07:00
mrg 8ece411954 Merge branch 'dev' into tech_migration 2020-04-16 11:32:02 -07:00
Aditi Sinha 2661a42726 changes to support spare columns 2020-04-14 03:09:10 +00:00
mrg 2e67d44cd7 First pass of multiple bitcells per decoder row 2020-04-10 13:29:41 -07:00
mrg 7888e54fc4 Remove dynamic bitcell multiple detection. 
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
 2020-04-09 11:38:18 -07:00
mrg 58fbc5351a Change rows to outputs in hierarchical decoder 2020-04-08 17:05:16 -07:00
mrg 7872b6a68c Merge branch 'dev' into tech_migration 2020-04-07 10:42:05 -07:00
mrg cd8dc8e20b Output lvs model instead of spice model 2020-04-06 14:08:38 -07:00
mrg a12b5d9e6c Split decoder pbitcell tests 2020-04-06 13:31:31 -07:00
mrg f358de78bb Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation) 2020-04-03 13:39:54 -07:00
mrg f105c9ab36 Netlist only in verilog test 2020-04-02 12:43:19 -07:00
mrg 1d5e5e3607 Don't run lvs/drc or route supplies in verilog test 2020-04-02 12:42:28 -07:00
mrg a3683c5898 Separate pbitcell from hierarchical decoder 2020-04-01 16:39:47 -07:00
mrg 3e41664db6 Split precharge array to multiport and normal cell 2020-04-01 11:26:31 -07:00
mrg da334e47aa Separate pbitcell tests for precharge 2020-04-01 11:14:50 -07:00
Joey Kunzler b0d2946c80 update to sense amp and write driver modules 2020-03-30 20:00:32 -07:00
mrg c15b4167b6 Merge branch 'dev' into tech_migration 2020-03-23 11:57:03 -07:00
mrg f21791a904 Add source drain contact options to ptx. 2020-03-23 11:36:45 -07:00
Aditi Sinha b75eeb7688 Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
mrg fd7af7fc25 Matt sucks skip test 2020-03-06 15:03:31 -08:00
Aditi Sinha 694ea5c20e Characterization for extra rows 2020-02-20 17:31:58 +00:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
Aditi Sinha 88bc1f09cb Characterization for extra rows 2020-02-20 17:01:52 +00:00
mrg 5aed893725 Add nwell/pwell tap test 2020-02-03 18:41:06 +00:00
Matt Guthaus b7d78ec2ec Fix ptx active contact orientation to non-default M1 direction. 2019-12-19 12:54:10 -08:00
Matthew Guthaus fc4685c7f7 Cleanup. 2019-12-17 23:07:01 +00:00
Matthew Guthaus 449b0a7c28 Make wire test programmatic 2019-12-17 22:36:38 +00:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus d3a2c46cb9 Remove some contact tests 2019-12-16 17:15:29 -08:00
Matt Guthaus 6058af994c Fix ignore gds files 2019-12-16 15:39:32 -08:00
Matt Guthaus 3eb0dad06a Remove cells from DRC/LVS in the blackbox tech list. 2019-12-16 15:33:30 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Matt Guthaus e048ada23c Abstract basic DRC checks 2019-12-11 17:56:55 -08:00
Matthew Guthaus 8f473b26a9 Add replica bitcell test for 1 port 2019-12-05 01:14:06 +00:00
Matthew Guthaus d519c00aa1 Fix contact order in test 2019-12-05 01:06:31 +00:00
Matt Guthaus 7b9e7ff35b Nominal corner only for sim tests. Netlist only for speed. 2019-11-30 12:48:25 -08:00
Matt Guthaus 6ef1b6a4ec Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
Matt Guthaus 2a912dab7a Remove unused config files 2019-11-29 12:35:35 -08:00
Matt Guthaus 0cdd3af1aa Change default nominal corners to false and enable in test config. 2019-11-29 12:08:53 -08:00
Matt Guthaus d511f648c6 Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
Matt Guthaus f4599b7121 Default tools are calibre except for SCMOS 2019-11-26 13:23:18 -08:00
Matt Guthaus 190c5a078e Fix permissions on pwrite_driver test 2019-11-20 11:49:39 -08:00
Matt Guthaus 3364f47e56 Fix wrong supply voltage in config files. 2019-11-20 09:50:27 -08:00
Matthew Guthaus cdf01c6c23 Fix test 30 for generic configs 2019-11-17 00:49:38 +00:00
Matthew Guthaus b3fb4e3183 Make unit test configs generic to tech_name 2019-11-17 00:44:31 +00:00
Matthew Guthaus b3b3cf0210 Merge remote-tracking branch 'origin/dev' into tech_migration 2019-11-17 00:15:18 +00:00
Matthew Guthaus aca99b87bc Fix config for tests 30 2019-11-16 22:22:30 +00:00
Matthew Guthaus c4cf8134fe Undo changes for config expansion. Change unit tests to use OPENRAM_HOME. 2019-11-15 18:47:59 +00:00
Aditi Sinha 2c7aa5d0da Non-power of 2 address decode tentative 2019-11-15 03:59:57 +00:00
Matthew Guthaus 04af5480d2 Add skeleton files for pwrite_driver 2019-10-30 21:34:03 +00:00
Matt Guthaus 764d4da1bd Clean up config file organization. Improve gdsMill debug output. 2019-10-23 10:48:18 -07:00
Hunter Nichols b420f77ff1 Updated leakage power golden data in hspice delay test. 2019-10-01 15:26:34 -07:00
Hunter Nichols 19a09470d4 Merged with dev, conflict in golden data of hspice delay test. 2019-10-01 14:26:34 -07:00
Hunter Nichols 7b029a4582 Updated golden values in delay tests due to model changes. 2019-09-30 14:02:00 -07:00
Matt Guthaus b0dcfb5b2d Fix leakage mismatch in results. 2019-09-27 15:14:01 -07:00
Matt Guthaus 585ce63dff Removing unused tech parms. Simplifying redundant parms. 2019-09-04 16:08:18 -07:00
Matt Guthaus 8c601ce939 Model tests don't need layout 2019-09-04 16:06:12 -07:00
Matt Guthaus c5568e86fe Enable spice and don't purge option to test 30 2019-09-04 14:33:25 -07:00
Matt Guthaus eadb5d5e48 Allow gds file for front end with new options 2019-09-04 10:26:54 -07:00
jsowash 1a72070f04 Removed LVS error where w_en went over whole AND array in 2 port. 2019-09-03 17:14:31 -07:00
jsowash 4c40804b8f Moved via in write driver up for 2 port. 2019-09-03 15:14:41 -07:00
jsowash abb86c338b Added port specification. 2019-09-03 14:52:43 -07:00
jsowash 4a8ec7a687 Added 2 port test for wmask. 2019-09-03 11:49:37 -07:00
jsowash e8435d0d83 Added test for picorv32 memory without characterization. 2019-08-30 11:24:20 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus 2ffdfb18a4 Fix trunks less than a pitch in channel route 2019-08-21 17:11:02 -07:00
jsowash a8df5528f9 Added 2 mux test for wmask. 2019-08-21 16:06:36 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
Matt Guthaus f2568fec80 Change permissions on tests to +x. Add single bank wmask test. 2019-08-21 08:49:46 -07:00
jsowash a28c9fed8b Fixed bug for more than 2 wmasks and changed test to test 4 wmasks. 2019-08-16 14:27:44 -07:00
jsowash d02ea06ff2 Added method to route between the output of wmask AND array and en of write driver. 2019-08-16 14:12:41 -07:00
jsowash f0f811bad9 Added a condiitonal to only route wmask dff when there's a write size. 2019-08-14 12:40:14 -07:00
jsowash 858fbb062d Placed wmask dff and added connections for wmask pins. 2019-08-14 11:45:22 -07:00
jsowash 0d7170eb95 Created wmask AND array en pin to go through to top layer. 2019-08-14 09:59:40 -07:00
jsowash aa4803f3c4 Increased enable pin's width for larger # of column mux ways. 2019-08-11 15:25:05 -07:00
jsowash 2573b5f48b Fixed merge conflict. 2019-08-11 14:39:36 -07:00
Matt Guthaus d56a972d61 Update ngspice tests due to new version 2019-08-10 17:59:30 -07:00
jsowash d5e331d4f3 Connected en together in write_mask_and_array. 2019-08-09 14:27:53 -07:00
Hunter Nichols 1d22d39667 Uncommented tests that use model delays. Fixed issue in sense amp cin. 2019-08-08 18:26:12 -07:00
jsowash 49fffcbc92 Added way to determine length of en pin with wmask in write_driver_array and shortened en to width of driver. 2019-08-08 15:49:23 -07:00
jsowash 0cfa0ac755 Shortened write driver enable pin so that a write mask can be used without a col mux in layout. 2019-08-08 12:57:32 -07:00
Matt Guthaus 275891084b Add pand3 2019-08-07 16:33:29 -07:00
jsowash 9409f60237 Merge branch 'dev' into add_wmask 2019-08-07 09:42:55 -07:00
jsowash a6bb410560 Begin implementing a write mask layout as the port data level. 2019-08-07 09:12:21 -07:00
Matt Guthaus c3f38a5cac ngspice delays updated (again) 2019-08-05 16:09:27 -07:00
Matt Guthaus aae8566ff2 Update golden delays. Fix uninitialized boolean. 2019-08-05 15:45:59 -07:00
Matt Guthaus 4d11de64ac Additional debug. Smaller psram func tests. 2019-08-05 13:53:14 -07:00
jsowash bb1627bcec Added test to end of w_mask_and_array so a regression test will be performed on it. 2019-07-31 14:59:33 -07:00
jsowash 774f08da51 Added layout pins to and test for write_mask_and_array. 2019-07-31 14:11:37 -07:00
Matt Guthaus 8e43469486 Update spice results 2019-07-27 12:13:44 -07:00
Matt Guthaus d7bc3e8207 Add dummy pbitcell 2019-07-27 12:13:35 -07:00
Matt Guthaus fa4f98b122 Fix ALL of the indents. 2019-07-27 11:30:48 -07:00
Matt Guthaus 37fffb2ed2 Fix bad indent. 2019-07-27 11:14:56 -07:00
Matt Guthaus 468a759d1e Fixed control problems (probably) 
Extended functional tests for 15 cycles (slow, but more checking)
Fixed s_en to be gated AFTER the RBL.
 2019-07-27 11:09:08 -07:00
Matt Guthaus 179efe4d04 Fix bitline names in merge error 2019-07-26 22:03:50 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus 8ebc568e8b Minor cleanup. Skip more tests until analytical fixed. 2019-07-26 08:33:06 -07:00
Matt Guthaus 20d9c30a64 Use non-analytical models for now 2019-07-25 14:55:42 -07:00
Matt Guthaus 88c399bc6c Skip prune test for now 2019-07-25 14:49:11 -07:00
Matt Guthaus d5419f99f6 Skip model tests for now 2019-07-25 14:46:33 -07:00
Matt Guthaus c8c4d05bba Fix some regression fails. 2019-07-25 14:18:08 -07:00
jsowash 61ba23706c Removed comments for rw pen() and added a wmask func test. 2019-07-25 12:24:27 -07:00
jsowash a69d35b50a Removed write_size from parameters. 2019-07-21 15:53:05 -07:00
jsowash 0a5461201a Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
jsowash 45cb159d7f Connected wmask in the spice netlist. 2019-07-19 13:17:55 -07:00
Matt Guthaus 864639d96e Remove old replica bitline. 2019-07-18 15:19:40 -07:00
Matt Guthaus a707c6fa50 Convert psram tests to only 2 port. 2019-07-18 14:49:54 -07:00
jsowash 720739a192 Skipping test 22_sram_wmask_func_test and changed a typo of write_driver to write_mask 2019-07-17 11:04:17 -07:00
mrg 12fa36317e Cleanup unit test. Fix s_en control bug for r-only. 2019-07-16 13:51:31 -07:00
mrg 70ee026fcf Add cell names to psingle_bank test 2019-07-16 11:54:57 -07:00
mrg 42ad0cd282 Add pbitcell RW test 2019-07-16 11:54:39 -07:00
mrg 37c15937e2 Add multiple control logic port types. 2019-07-15 17:07:50 -07:00
jsowash 021d604832 Removed wmask from addwrite() 2019-07-15 16:48:36 -07:00
jsowash ab27c70279 Merge branch 'dev' into add_wmask 2019-07-15 14:42:23 -07:00
mrg e550d6ff10 Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
mrg 8815ddf7f1 Remove unnecessary feasible period search. 2019-07-12 11:55:42 -07:00
mrg 9092fa4ee6 Remove multiport control logic test since it doesn't have a bitcell anymore. 2019-07-12 11:18:47 -07:00
mrg a189b325ed Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
mrg 80145c0a92 Only enable pdb post-mortem when not purging temp for debug. 2019-07-12 10:57:59 -07:00
mrg 17d144b5b5 Clean up multiport test options to be consistent. 2019-07-12 10:39:55 -07:00
jsowash dfa2b29b8f Begin adding wmask netlist and spice tests. 2019-07-12 10:34:29 -07:00
mrg aa552f8e96 Remove debug trace 2019-07-12 10:17:33 -07:00
mrg 043018e8ba Functional tests working with new RBL. 2019-07-12 08:42:36 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
Bin Wu c9c839ca46 fix the delay measure bug in pex tests 2019-07-10 04:39:40 -07:00
Bin Wu e4070ddad8 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2 2019-07-10 03:09:12 -07:00
jsowash 24bfaa3b76 Added write_size to test 16 and added a newline to Verilog with no wmask for test 25. 2019-07-05 15:55:03 -07:00
jsowash ad9193ad5a Verified 1rw mask writing and changed verilog.py accordingly. 2019-07-05 15:08:59 -07:00
mrg 9dab0be737 Single bank working with replica array. 2019-07-05 13:44:29 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
Matt Guthaus f914ab0ece Re-enable replica tests 2019-07-03 14:57:47 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
mrg 70c83f20b6 Fixes to pass unit tests. 
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
 2019-07-03 13:37:56 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
mrg 244604fb0d Data port module working by itself. 2019-07-02 15:35:53 -07:00
Bin Wu 9ce968b446 megre with dev changes 2019-06-30 00:50:18 -07:00