mirror of https://github.com/VLSIDA/OpenRAM.git
Change default nominal corners to false and enable in test config.
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d511f648c6
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@ -2,6 +2,7 @@ word_size = 32
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num_words = 128
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tech_name = "scn4m_subm"
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nominal_corners_only = False
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process_corners = ["TT"]
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supply_voltages = [5.0]
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temperatures = [25]
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@ -9,6 +10,3 @@ temperatures = [25]
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output_path = "temp"
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output_name = "sram_{0}_{1}_{2}".format(word_size, num_words, tech_name)
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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@ -6,6 +6,7 @@ num_r_ports = 1
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num_w_ports = 0
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tech_name = "scn4m_subm"
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nominal_corners_only = False
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process_corners = ["TT"]
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supply_voltages = [5.0]
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temperatures = [25]
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@ -17,7 +18,3 @@ output_path = "temp"
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output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size,
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num_words,
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tech_name)
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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@ -6,6 +6,7 @@ num_r_ports = 1
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num_w_ports = 0
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tech_name = "scn4m_subm"
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nominal_corners_only = False
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process_corners = ["TT"]
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supply_voltages = [5.0]
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temperatures = [25]
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@ -2,6 +2,7 @@ word_size = 2
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num_words = 16
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tech_name = "freepdk45"
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nominal_corners_only = False
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process_corners = ["TT"]
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supply_voltages = [1.0]
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temperatures = [25]
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@ -2,6 +2,7 @@ word_size = 2
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num_words = 16
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tech_name = "scn4m_subm"
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nominal_corners_only = False
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process_corners = ["TT"]
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supply_voltages = [5.0]
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temperatures = [25]
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@ -14,6 +15,3 @@ output_name = "sram_{0}_{1}_{2}".format(word_size,
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num_words,
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tech_name)
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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@ -2,6 +2,7 @@ word_size = 64
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num_words = 1024
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tech_name = "scn4m_subm"
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nominal_corners_only = False
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process_corners = ["TT"]
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supply_voltages = [ 5.0 ]
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temperatures = [ 25 ]
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@ -10,7 +11,3 @@ output_path = "temp"
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output_name = "sram_{0}_{1}_{2}".format(word_size,
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num_words,
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tech_name)
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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@ -2,8 +2,9 @@ word_size = 16
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num_words = 256
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tech_name = "scn4m_subm"
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nominal_corners_only = False
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process_corners = ["TT"]
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supply_voltages = [3.3]
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supply_voltages = [5.0]
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temperatures = [25]
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output_path = "temp"
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@ -11,6 +12,3 @@ output_name = "sram_{0}_{1}_{2}".format(word_size,
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num_words,
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tech_name)
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drc_name = "magic"
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lvs_name = "netgen"
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pex_name = "magic"
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@ -34,7 +34,7 @@ class options(optparse.Values):
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write_size = None
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# These will get initialized by the user or the tech file
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nominal_corner_only = True
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nominal_corner_only = False
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supply_voltages = ""
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temperatures = ""
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process_corners = ""
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@ -11,6 +11,7 @@ num_words = 16
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tech_name = OPTS.tech_name
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nominal_corner_only = True
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route_supplies = True
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check_lvsdrc = True
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@ -11,6 +11,7 @@ num_words = 16
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tech_name = OPTS.tech_name
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nominal_corner_only = True
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route_supplies = True
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check_lvsdrc = True
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inline_lvsdrc = True
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@ -11,4 +11,3 @@ num_words = 16
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tech_name = OPTS.tech_name
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