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Fix capitalization in verilog golden files

This commit is contained in:
Matt Guthaus 2019-08-21 14:29:57 -07:00
parent 5f3ffdb8ba
commit 9f54afbf2c
12 changed files with 54 additions and 54 deletions
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24
compiler/base/verilog.py
View File

@ -22,7 +22,7 @@ class verilog:
self.vf.write("// OpenRAM SRAM model\n")
self.vf.write("// Words: {0}\n".format(self.num_words))
self.vf.write("// Word size: {0}\n".format(self.word_size))
if self.write_size is not None:
if self.write_size:
self.vf.write("// Write size: {0}\n\n".format(self.write_size))
else:
self.vf.write("\n")
@ -37,12 +37,12 @@ class verilog:
self.vf.write("// Port {0}: W\n".format(port))
if port in self.readwrite_ports:
self.vf.write(" clk{0},csb{0},web{0},".format(port))
if self.write_size is not None:
if self.write_size:
self.vf.write("wmask{},".format(port))
self.vf.write("addr{0},din{0},dout{0}".format(port))
elif port in self.write_ports:
self.vf.write(" clk{0},csb{0},".format(port))
if self.write_size is not None:
if self.write_size:
self.vf.write("wmask{},".format(port))
self.vf.write("addr{0},din{0}".format(port))
elif port in self.read_ports:
@ -52,7 +52,7 @@ class verilog:
self.vf.write(",\n")
self.vf.write("\n );\n\n")
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
self.vf.write(" parameter NUM_WMASKS = {0} ;\n".format(self.num_wmasks))
self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size))
@ -99,7 +99,7 @@ class verilog:
if port in self.readwrite_ports:
self.vf.write(" reg web{0}_reg;\n".format(port))
if port in self.write_ports:
if self.write_size is not None:
if self.write_size:
self.vf.write(" reg [NUM_WMASKS-1:0] wmask{0}_reg;\n".format(port))
self.vf.write(" reg [ADDR_WIDTH-1:0] addr{0}_reg;\n".format(port))
if port in self.write_ports:
@ -119,7 +119,7 @@ class verilog:
if port in self.readwrite_ports:
self.vf.write(" web{0}_reg = web{0};\n".format(port))
if port in self.write_ports:
if self.write_size is not None:
if self.write_size:
self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port))
self.vf.write(" addr{0}_reg = addr{0};\n".format(port))
if port in self.write_ports:
@ -134,13 +134,13 @@ class verilog:
self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))
if port in self.readwrite_ports:
self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port))
if self.write_size is not None:
if self.write_size:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port))
else:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b\",addr{0}_reg,din{0}_reg);\n".format(port))
elif port in self.write_ports:
self.vf.write(" if ( !csb{0}_reg )\n".format(port))
if self.write_size is not None:
if self.write_size:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port))
else:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b\",addr{0}_reg,din{0}_reg);\n".format(port))
@ -156,7 +156,7 @@ class verilog:
self.vf.write(" input csb{0}; // active low chip select\n".format(port))
if port in self.readwrite_ports:
self.vf.write(" input web{0}; // active low write control\n".format(port))
if self.write_size is not None:
if self.write_size:
self.vf.write(" input [NUM_WMASKS-1:0] wmask{0}; // write mask\n".format(port))
self.vf.write(" input [ADDR_WIDTH-1:0] addr{0};\n".format(port))
if port in self.write_ports:
@ -175,17 +175,17 @@ class verilog:
self.vf.write(" always @ (negedge clk{0})\n".format(port))
self.vf.write(" begin : MEM_WRITE{0}\n".format(port))
if port in self.readwrite_ports:
if self.write_size is not None:
if self.write_size:
self.vf.write(" if ( !csb{0}_reg && !web{0}_reg ) begin\n".format(port))
else:
self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port))
else:
if self.write_size is not None:
if self.write_size:
self.vf.write(" if (!csb{0}_reg) begin\n".format(port))
else:
self.vf.write(" if (!csb{0}_reg)\n".format(port))
if self.write_size is not None:
if self.write_size:
for mask in range(0,self.num_wmasks):
lower = mask * self.write_size
upper = lower + self.write_size-1

2
compiler/characterizer/delay.py
View File

@ -46,7 +46,7 @@ class delay(simulation):
self.targ_read_ports = []
self.targ_write_ports = []
self.period = 0
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size / self.write_size)
else:
self.num_wmasks = 0

8
compiler/characterizer/functional.py
View File

@ -34,7 +34,7 @@ class functional(simulation):
if OPTS.is_unit_test:
random.seed(12345)
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size / self.write_size)
else:
self.num_wmasks = 0
@ -61,7 +61,7 @@ class functional(simulation):
def initialize_wmask(self):
self.wmask = ""
if self.write_size is not None:
if self.write_size:
# initialize all wmask bits to 1
for bit in range(self.num_wmasks):
self.wmask += "1"
@ -85,7 +85,7 @@ class functional(simulation):
return self.check_stim_results()
def write_random_memory_sequence(self):
if self.write_size is not None:
if self.write_size:
rw_ops = ["noop", "write", "partial_write", "read"]
w_ops = ["noop", "write", "partial_write"]
else:
@ -340,7 +340,7 @@ class functional(simulation):
# Generate wmask bits
for port in self.write_ports:
if self.write_size is not None:
if self.write_size:
self.sf.write("\n* Generation of wmask signals\n")
for bit in range(self.num_wmasks):
sig_name = "WMASK{0}_{1} ".format(port, bit)

4
compiler/characterizer/simulation.py
View File

@ -31,7 +31,7 @@ class simulation():
self.readwrite_ports = self.sram.readwrite_ports
self.read_ports = self.sram.read_ports
self.write_ports = self.sram.write_ports
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
@ -303,7 +303,7 @@ class simulation():
for port in range(total_ports):
pin_names.append("{0}{1}".format(tech.spice["clk"], port))
if self.write_size is not None:
if self.write_size:
for port in write_index:
for bit in range(self.num_wmasks):
pin_names.append("WMASK{0}_{1}".format(port,bit))

2
compiler/modules/bank.py
View File

@ -30,7 +30,7 @@ class bank(design.design):
self.sram_config = sram_config
sram_config.set_local_config(self)
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0

2
compiler/modules/multibank.py
View File

@ -187,7 +187,7 @@ class multibank(design.design):
words_per_row=self.words_per_row)
self.add_mod(self.sense_amp_array)
if self.write_size is not None:
if self.write_size:
self.write_mask_driver_array = self.mod_write_mask_driver_array(columns=self.num_cols,
word_size=self.word_size,
write_size=self.write_size)

8
compiler/modules/port_data.py
View File

@ -22,7 +22,7 @@ class port_data(design.design):
sram_config.set_local_config(self)
self.port = port
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
@ -58,7 +58,7 @@ class port_data(design.design):
if self.write_driver_array:
self.create_write_driver_array()
if self.write_size is not None:
if self.write_size:
self.create_write_mask_and_array()
else:
self.write_mask_and_array_inst = None
@ -183,7 +183,7 @@ class port_data(design.design):
word_size=self.word_size,
write_size=self.write_size)
self.add_mod(self.write_driver_array)
if self.write_size is not None:
if self.write_size:
self.write_mask_and_array = factory.create(module_type="write_mask_and_array",
columns=self.num_cols,
word_size=self.word_size,
@ -316,7 +316,7 @@ class port_data(design.design):
temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
if self.write_size is not None:
if self.write_size:
for i in range(self.num_wmasks):
temp.append("wdriver_sel_{}".format(i))
else:

4
compiler/modules/write_driver_array.py
View File

@ -30,7 +30,7 @@ class write_driver_array(design.design):
self.write_size = write_size
self.words_per_row = int(columns / word_size)
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
self.create_netlist()
@ -89,7 +89,7 @@ class write_driver_array(design.design):
self.driver_insts[index]=self.add_inst(name=name,
mod=self.driver)
if self.write_size is not None:
if self.write_size:
self.connect_inst(["data_{0}".format(index),
"bl_{0}".format(index),
"br_{0}".format(index),

10
compiler/sram/sram_1bank.py
View File

@ -46,7 +46,7 @@ class sram_1bank(sram_base):
self.data_dff_insts = self.create_data_dff()
if self.write_size is not None:
if self.write_size:
self.wmask_dff_insts = self.create_wmask_dff()
@ -126,7 +126,7 @@ class sram_1bank(sram_base):
self.data_dff_insts[port].place(data_pos[port])
# Add the write mask flops to the left of the din flops.
if self.write_size is not None:
if self.write_size:
if port in self.write_ports:
wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width,
-max_gap_size - self.wmask_dff_insts[port].height)
@ -148,7 +148,7 @@ class sram_1bank(sram_base):
self.data_dff_insts[port].place(data_pos[port], mirror="MX")
# Add the write mask flops to the left of the din flops.
if self.write_size is not None:
if self.write_size:
if port in self.write_ports:
wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
self.bank.height + max_gap_size + self.data_dff_insts[port].height)
@ -190,7 +190,7 @@ class sram_1bank(sram_base):
self.data_dff_insts[port].place(data_pos[port], mirror="MX")
# Add the write mask flops to the left of the din flops.
if self.write_size is not None:
if self.write_size:
if port in self.write_ports:
wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
self.bank.height + max_gap_size + self.data_dff_insts[port].height)
@ -386,7 +386,7 @@ class sram_1bank(sram_base):
#Data dffs and wmask dffs are only for writing so are not useful for evaluating read delay.
for inst in self.data_dff_insts:
self.graph_inst_exclude.add(inst)
if self.write_size is not None:
if self.write_size:
for inst in self.wmask_dff_insts:
self.graph_inst_exclude.add(inst)

4
compiler/sram/sram_base.py
View File

@ -35,7 +35,7 @@ class sram_base(design, verilog, lef):
self.bank_insts = []
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
@ -284,7 +284,7 @@ class sram_base(design, verilog, lef):
self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size)
self.add_mod(self.data_dff)
if self.write_size is not None:
if self.write_size:
self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=self.num_wmasks)
self.add_mod(self.wmask_dff)

20
compiler/tests/golden/sram_2_16_1_freepdk45.v
View File

@ -7,24 +7,24 @@ module sram_2_16_1_freepdk45(
clk0,csb0,web0,addr0,din0,dout0
);
parameter data_WIDTH = 2 ;
parameter addr_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << addr_WIDTH;
parameter DATA_WIDTH = 2 ;
parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3 ;
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [addr_WIDTH-1:0] addr0;
input [data_WIDTH-1:0] din0;
output [data_WIDTH-1:0] dout0;
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [addr_WIDTH-1:0] addr0_reg;
reg [data_WIDTH-1:0] din0_reg;
reg [data_WIDTH-1:0] dout0;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0)
@ -40,7 +40,7 @@ module sram_2_16_1_freepdk45(
$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
end
reg [data_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0

20
compiler/tests/golden/sram_2_16_1_scn4m_subm.v
View File

@ -7,24 +7,24 @@ module sram_2_16_1_scn4m_subm(
clk0,csb0,web0,addr0,din0,dout0
);
parameter data_WIDTH = 2 ;
parameter addr_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << addr_WIDTH;
parameter DATA_WIDTH = 2 ;
parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3 ;
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [addr_WIDTH-1:0] addr0;
input [data_WIDTH-1:0] din0;
output [data_WIDTH-1:0] dout0;
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [addr_WIDTH-1:0] addr0_reg;
reg [data_WIDTH-1:0] din0_reg;
reg [data_WIDTH-1:0] dout0;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0)
@ -40,7 +40,7 @@ module sram_2_16_1_scn4m_subm(
$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
end
reg [data_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0