Blackbox option for DRC waivers

compiler/options.py

@@ -86,8 +86,6 @@ class options(optparse.Values):
     check_lvsdrc = False
     # This determines whether LVS and DRC is checked for every submodule.
     inline_lvsdrc = False
-    # Treat the bitcell as a black box (no DRC, LVS, or extraction)
-    blackbox_bitcell = False
     # Remove noncritical memory cells for characterization speed-up
     trim_netlist = False
     # Run with extracted parasitics

compiler/tests/01_library_drc_test.py

@@ -42,6 +42,11 @@ def setup_files():
     files = os.listdir(gds_dir)
     nametest = re.compile("\.gds$", re.IGNORECASE)
     gds_files = list(filter(nametest.search, files))
+    import tech
+    if tech.blackbox_bitcell:
+        # Ignore DRC of all bitcells
+        nametest = re.compile("cell", re.IGNORECASE)
+        gds_files = list(filter(lambda v: not nametest.search(v), gds_files))
     return (gds_dir, gds_files)
 
 

technology/freepdk45/tech/tech.py

@@ -344,6 +344,8 @@ drc_name = "calibre"
 lvs_name = "calibre"
 pex_name = "calibre"
 
+blackbox_bitcell = False
+
 ###################################################
 ##END Technology Tool Preferences
 ###################################################

technology/scn4m_subm/tech/tech.py

@@ -310,6 +310,8 @@ drc_name = "magic"
 lvs_name = "netgen"
 pex_name = "magic"
 
+blackbox_bitcell = False
+
 ###################################################
 ##END Technology Tool Preferences
 ###################################################