mirror of https://github.com/VLSIDA/OpenRAM.git
Non-power of 2 address decode tentative
This commit is contained in:
Aditi Sinha
parent
04af5480d2
commit
2c7aa5d0da
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@ -10,6 +10,7 @@ import debug
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import design
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from math import log
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from math import sqrt
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from math import ceil
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import math
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import contact
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from sram_factory import factory
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@ -31,7 +32,7 @@ class hierarchical_decoder(design.design):
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self.cell_height = height
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self.rows = rows
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self.num_inputs = int(math.log(self.rows, 2))
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self.num_inputs = math.ceil(math.log(self.rows, 2))
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(self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
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self.create_netlist()
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@ -338,14 +339,15 @@ class hierarchical_decoder(design.design):
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for i in range(len(self.predec_groups[0])):
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for j in range(len(self.predec_groups[1])):
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row = len(self.predec_groups[0])*j + i
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name = self.NAND_FORMAT.format(row)
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self.nand_inst.append(self.add_inst(name=name,
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mod=self.nand2))
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pins =["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"Z_{0}".format(row),
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"vdd", "gnd"]
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self.connect_inst(pins)
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if (row < self.rows):
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name = self.NAND_FORMAT.format(row)
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self.nand_inst.append(self.add_inst(name=name,
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mod=self.nand2))
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pins =["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"Z_{0}".format(row),
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"vdd", "gnd"]
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self.connect_inst(pins)
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# Row Decoder NAND GATE array for address inputs >5.
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@ -356,16 +358,17 @@ class hierarchical_decoder(design.design):
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row = (len(self.predec_groups[0])*len(self.predec_groups[1])) * k \
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+ len(self.predec_groups[0])*j + i
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name = self.NAND_FORMAT.format(row)
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self.nand_inst.append(self.add_inst(name=name,
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mod=self.nand3))
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if (row < self.rows):
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name = self.NAND_FORMAT.format(row)
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self.nand_inst.append(self.add_inst(name=name,
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mod=self.nand3))
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pins = ["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])),
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"Z_{0}".format(row),
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"vdd", "gnd"]
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self.connect_inst(pins)
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pins = ["out_{0}".format(i),
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"out_{0}".format(j + len(self.predec_groups[0])),
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"out_{0}".format(k + len(self.predec_groups[0]) + len(self.predec_groups[1])),
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"Z_{0}".format(row),
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"vdd", "gnd"]
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self.connect_inst(pins)
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def create_decoder_inv_array(self):
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@ -527,10 +530,11 @@ class hierarchical_decoder(design.design):
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for index_B in self.predec_groups[1]:
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for index_A in self.predec_groups[0]:
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# FIXME: convert to connect_bus?
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B"))
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if (row_index < self.rows):
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B"))
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row_index = row_index + 1
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elif (self.num_inputs > 5):
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@ -538,12 +542,13 @@ class hierarchical_decoder(design.design):
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for index_B in self.predec_groups[1]:
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for index_A in self.predec_groups[0]:
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# FIXME: convert to connect_bus?
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B"))
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predecode_name = "predecode_{}".format(index_C)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("C"))
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if (row_index < self.rows):
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predecode_name = "predecode_{}".format(index_A)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("A"))
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predecode_name = "predecode_{}".format(index_B)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("B"))
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predecode_name = "predecode_{}".format(index_C)
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self.route_predecode_rail(predecode_name, self.nand_inst[row_index].get_pin("C"))
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row_index = row_index + 1
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def route_vdd_gnd(self):
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@ -34,14 +34,30 @@ class hierarchical_decoder_test(openram_test):
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a = factory.create(module_type="hierarchical_decoder", rows=16)
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self.local_check(a)
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debug.info(1, "Testing 17 row sample for hierarchical_decoder")
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a = factory.create(module_type="hierarchical_decoder", rows=17)
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self.local_check(a)
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debug.info(1, "Testing 23 row sample for hierarchical_decoder")
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a = factory.create(module_type="hierarchical_decoder", rows=23)
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self.local_check(a)
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debug.info(1, "Testing 32 row sample for hierarchical_decoder")
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a = factory.create(module_type="hierarchical_decoder", rows=32)
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self.local_check(a)
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debug.info(1, "Testing 65 row sample for hierarchical_decoder")
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a = factory.create(module_type="hierarchical_decoder", rows=65)
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self.local_check(a)
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debug.info(1, "Testing 128 row sample for hierarchical_decoder")
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a = factory.create(module_type="hierarchical_decoder", rows=128)
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self.local_check(a)
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debug.info(1, "Testing 341 row sample for hierarchical_decoder")
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a = factory.create(module_type="hierarchical_decoder", rows=341)
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self.local_check(a)
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debug.info(1, "Testing 512 row sample for hierarchical_decoder")
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a = factory.create(module_type="hierarchical_decoder", rows=512)
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self.local_check(a)
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@ -57,14 +73,34 @@ class hierarchical_decoder_test(openram_test):
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a = factory.create(module_type="hierarchical_decoder", rows=16)
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self.local_check(a)
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factory.reset()
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debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)")
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a = factory.create(module_type="hierarchical_decoder", rows=17)
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self.local_check(a)
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factory.reset()
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debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)")
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a = factory.create(module_type="hierarchical_decoder", rows=23)
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self.local_check(a)
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debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
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a = factory.create(module_type="hierarchical_decoder", rows=32)
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self.local_check(a)
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factory.reset()
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debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)")
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a = factory.create(module_type="hierarchical_decoder", rows=65)
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self.local_check(a)
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debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
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a = factory.create(module_type="hierarchical_decoder", rows=128)
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self.local_check(a)
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factory.reset()
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debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)")
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a = factory.create(module_type="hierarchical_decoder", rows=341)
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self.local_check(a)
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debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
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a = factory.create(module_type="hierarchical_decoder", rows=512)
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self.local_check(a)
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