mirror of https://github.com/VLSIDA/OpenRAM.git
Merged with dev, conflict in golden data of hspice delay test.
This commit is contained in:
Hunter Nichols
commit
19a09470d4
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@ -122,6 +122,9 @@ class verilog:
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if self.write_size:
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self.vf.write(" wmask{0}_reg = wmask{0};\n".format(port))
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self.vf.write(" addr{0}_reg = addr{0};\n".format(port))
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if port in self.read_ports:
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self.add_write_read_checks(port)
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if port in self.write_ports:
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self.vf.write(" din{0}_reg = din{0};\n".format(port))
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if port in self.read_ports:
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@ -211,4 +214,29 @@ class verilog:
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self.vf.write(" if (!csb{0}_reg)\n".format(port))
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self.vf.write(" dout{0} <= #(DELAY) mem[addr{0}_reg];\n".format(port))
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self.vf.write(" end\n")
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def add_address_check(self, wport, rport):
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""" Output a warning if the two addresses match """
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# If the rport is actually reading... and addresses match.
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if rport in self.readwrite_ports:
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rport_control = "!csb{0} && web{0}".format(rport)
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else:
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rport_control = "!csb{0}".format(rport)
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if wport in self.readwrite_ports:
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wport_control = "!csb{0} && !web{0}".format(wport)
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else:
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wport_control = "!csb{0}".format(wport)
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self.vf.write(" if ({1} && {3} && (addr{0} == addr{2}))\n".format(wport,wport_control,rport,rport_control))
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self.vf.write(" $display($time,\" WARNING: Writing and reading addr{0}=%b and addr{1}=%b simultaneously!\",addr{0},addr{1});\n".format(wport,rport))
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def add_write_read_checks(self, rport):
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"""
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Add a warning if we read from an address that we are currently writing.
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Can be fixed if we appropriately size the write drivers to do this .
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"""
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for wport in self.write_ports:
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if wport == rport:
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continue
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else:
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self.add_address_check(wport,rport)
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@ -1180,44 +1180,57 @@ class delay(simulation):
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wmask_zeroes = "0"*self.num_wmasks
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if self.t_current == 0:
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self.add_noop_all_ports("Idle cycle (no positive clock edge)",
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inverse_address, data_zeros,wmask_zeroes)
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self.add_noop_all_ports("Idle cycle (no positive clock edge)")
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self.add_write("W data 1 address {}".format(inverse_address),
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inverse_address,data_ones,wmask_ones,write_port)
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inverse_address,
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data_ones,
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wmask_ones,
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write_port)
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self.add_write("W data 0 address {} to write value".format(self.probe_address),
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self.probe_address,data_zeros,wmask_ones,write_port)
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self.probe_address,
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data_zeros,
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wmask_ones,
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write_port)
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self.measure_cycles[write_port][sram_op.WRITE_ZERO] = len(self.cycle_times)-1
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# This also ensures we will have a H->L transition on the next read
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self.add_read("R data 1 address {} to set dout caps".format(inverse_address),
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inverse_address,data_zeros,wmask_ones,read_port)
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inverse_address,
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read_port)
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self.add_read("R data 0 address {} to check W0 worked".format(self.probe_address),
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self.probe_address,data_zeros,wmask_ones,read_port)
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self.probe_address,
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read_port)
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self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times)-1
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)",
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inverse_address,data_zeros,wmask_zeroes)
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)")
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self.add_write("W data 1 address {} to write value".format(self.probe_address),
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self.probe_address,data_ones,wmask_ones,write_port)
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self.probe_address,
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data_ones,
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wmask_ones,
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write_port)
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self.measure_cycles[write_port][sram_op.WRITE_ONE] = len(self.cycle_times)-1
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self.add_write("W data 0 address {} to clear din caps".format(inverse_address),
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inverse_address,data_zeros,wmask_ones,write_port)
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inverse_address,
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data_zeros,
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wmask_ones,
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write_port)
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# This also ensures we will have a L->H transition on the next read
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self.add_read("R data 0 address {} to clear dout caps".format(inverse_address),
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inverse_address,data_zeros,wmask_ones,read_port)
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inverse_address,
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read_port)
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self.add_read("R data 1 address {} to check W1 worked".format(self.probe_address),
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self.probe_address,data_zeros,wmask_ones,read_port)
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self.probe_address,
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read_port)
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self.measure_cycles[read_port][sram_op.READ_ONE] = len(self.cycle_times)-1
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle))",
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self.probe_address,data_zeros,wmask_zeroes)
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle))")
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def get_available_port(self,get_read_port):
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@ -6,6 +6,7 @@
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# All rights reserved.
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#
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import sys,re,shutil
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import copy
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import collections
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from design import design
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import debug
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@ -49,28 +50,19 @@ class functional(simulation):
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self.create_graph()
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self.set_internal_spice_names()
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self.initialize_wmask()
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# Number of checks can be changed
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self.num_cycles = 15
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# This is to have ordered keys for random selection
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self.stored_words = collections.OrderedDict()
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self.write_check = []
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self.read_check = []
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self.read_results = []
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def initialize_wmask(self):
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self.wmask = ""
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if self.write_size:
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# initialize all wmask bits to 1
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for bit in range(self.num_wmasks):
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self.wmask += "1"
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def run(self, feasible_period=None):
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if feasible_period: #period defaults to tech.py feasible period otherwise.
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self.period = feasible_period
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# Generate a random sequence of reads and writes
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self.write_random_memory_sequence()
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self.create_random_memory_sequence()
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# Run SPICE simulation
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self.write_functional_stimulus()
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@ -83,8 +75,26 @@ class functional(simulation):
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# Check read values with written values. If the values do not match, return an error.
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return self.check_stim_results()
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def write_random_memory_sequence(self):
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def check_lengths(self):
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""" Do a bunch of assertions. """
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for port in self.all_ports:
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checks = []
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if port in self.read_ports:
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checks.append((self.addr_value[port],"addr"))
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if port in self.write_ports:
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checks.append((self.data_value[port],"data"))
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checks.append((self.wmask_value[port],"wmask"))
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for (val, name) in checks:
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debug.check(len(self.cycle_times)==len(val),
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"Port {2} lengths don't match. {0} clock values, {1} {3} values".format(len(self.cycle_times),
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len(val),
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port,
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name))
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def create_random_memory_sequence(self):
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if self.write_size:
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rw_ops = ["noop", "write", "partial_write", "read"]
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w_ops = ["noop", "write", "partial_write"]
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@ -92,35 +102,45 @@ class functional(simulation):
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rw_ops = ["noop", "write", "read"]
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w_ops = ["noop", "write"]
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r_ops = ["noop", "read"]
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rw_read_din_data = "0"*self.word_size
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check = 0
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# First cycle idle
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, self.wmask, 0, self.t_current)
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self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks)
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# Write at least once
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addr = self.gen_addr()
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word = self.gen_data()
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comment = self.gen_cycle_comment("write", word, addr, self.wmask, 0, self.t_current)
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self.add_write(comment, addr, word, self.wmask, 0)
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self.stored_words[addr] = word
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# First cycle idle is always an idle cycle
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, "0"*self.num_wmasks, 0, self.t_current)
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self.add_noop_all_ports(comment)
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# Read at least once. For multiport, it is important that one read cycle uses all RW and R port to read from the same address simultaniously.
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# This will test the viablilty of the transistor sizing in the bitcell.
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for port in self.all_ports:
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if port in self.write_ports:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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else:
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comment = self.gen_cycle_comment("read", word, addr, self.wmask, port, self.t_current)
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self.add_read_one_port(comment, addr, rw_read_din_data, "0"*self.num_wmasks, port)
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self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
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check += 1
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# 1. Write all the write ports first to seed a bunch of locations.
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for port in self.write_ports:
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addr = self.gen_addr()
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word = self.gen_data()
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comment = self.gen_cycle_comment("write", word, addr, "1"*self.num_wmasks, port, self.t_current)
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self.add_write_one_port(comment, addr, word, "1"*self.num_wmasks, port)
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self.stored_words[addr] = word
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# All other read-only ports are noops.
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for port in self.read_ports:
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if port not in self.write_ports:
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self.add_noop_one_port(port)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.check_lengths()
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# Perform a random sequence of writes and reads on random ports, using random addresses and random words
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# and random write masks (if applicable)
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# 2. Read at least once. For multiport, it is important that one
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# read cycle uses all RW and R port to read from the same
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# address simultaniously. This will test the viablilty of the
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# transistor sizing in the bitcell.
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for port in self.all_ports:
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if port in self.write_ports:
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self.add_noop_one_port(port)
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else:
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comment = self.gen_cycle_comment("read", word, addr, "0"*self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(word, port)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.check_lengths()
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# 3. Perform a random sequence of writes and reads on random
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# ports, using random addresses and random words and random
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# write masks (if applicable)
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for i in range(self.num_cycles):
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w_addrs = []
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for port in self.all_ports:
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@ -132,63 +152,79 @@ class functional(simulation):
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op = random.choice(r_ops)
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if op == "noop":
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addr = "0"*self.addr_size
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word = "0"*self.word_size
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wmask = "0" * self.num_wmasks
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self.add_noop_one_port(addr, word, wmask, port)
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self.add_noop_one_port(port)
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elif op == "write":
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addr = self.gen_addr()
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word = self.gen_data()
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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self.add_noop_one_port(port)
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else:
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comment = self.gen_cycle_comment("write", word, addr, self.wmask, port, self.t_current)
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self.add_write_one_port(comment, addr, word, self.wmask, port)
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word = self.gen_data()
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comment = self.gen_cycle_comment("write", word, addr, "1"*self.num_wmasks, port, self.t_current)
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self.add_write_one_port(comment, addr, word, "1"*self.num_wmasks, port)
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self.stored_words[addr] = word
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w_addrs.append(addr)
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elif op == "partial_write":
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# write only to a word that's been written to
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(addr,old_word) = self.get_data()
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word = self.gen_data()
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wmask = self.gen_wmask()
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new_word = word
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for bit in range(len(wmask)):
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# When the write mask's bits are 0, the old data values should appear in the new word
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# as to not overwrite the old values
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if wmask[bit] == "0":
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lower = bit * self.write_size
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upper = lower + self.write_size - 1
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new_word = new_word[:lower] + old_word[lower:upper+1] + new_word[upper + 1:]
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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self.add_noop_one_port(port)
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else:
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word = self.gen_data()
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wmask = self.gen_wmask()
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new_word = self.gen_masked_data(old_word, word, wmask)
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comment = self.gen_cycle_comment("partial_write", word, addr, wmask, port, self.t_current)
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self.add_write_one_port(comment, addr, word, wmask, port)
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self.stored_words[addr] = new_word
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w_addrs.append(addr)
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else:
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(addr,word) = random.choice(list(self.stored_words.items()))
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# cannot read from an address that is currently being written to
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# The write driver is not sized sufficiently to drive through the two
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# bitcell access transistors to the read port. So, for now, we do not allow
|
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# a simultaneous write and read to the same address on different ports. This
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# could be even more difficult with multiple simultaneous read ports.
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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self.add_noop_one_port(port)
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else:
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comment = self.gen_cycle_comment("read", word, addr, self.wmask, port, self.t_current)
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self.add_read_one_port(comment, addr, rw_read_din_data, "0"*self.num_wmasks, port)
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self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
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check += 1
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comment = self.gen_cycle_comment("read", word, addr, "0"*self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(word, port)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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# Last cycle idle needed to correctly measure the value on the second to last clock edge
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, self.wmask, 0, self.t_current)
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self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks)
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, "0"*self.num_wmasks, 0, self.t_current)
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self.add_noop_all_ports(comment)
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def gen_masked_data(self, old_word, word, wmask):
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""" Create the masked data word """
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# Start with the new word
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new_word = word
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# When the write mask's bits are 0, the old data values should appear in the new word
|
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# as to not overwrite the old values
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for bit in range(len(wmask)):
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if wmask[bit] == "0":
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lower = bit * self.write_size
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upper = lower + self.write_size - 1
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new_word = new_word[:lower] + old_word[lower:upper+1] + new_word[upper + 1:]
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|
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return new_word
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def add_read_check(self, word, port):
|
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""" Add to the check array to ensure a read works. """
|
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try:
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self.check
|
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except:
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self.check = 0
|
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self.read_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, self.check])
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self.check += 1
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def read_stim_results(self):
|
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# Extrat dout values from spice timing.lis
|
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for (word, dout_port, eo_period, check) in self.write_check:
|
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# Extract dout values from spice timing.lis
|
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for (word, dout_port, eo_period, check) in self.read_check:
|
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sp_read_value = ""
|
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for bit in range(self.word_size):
|
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value = parse_spice_list("timing", "v{0}.{1}ck{2}".format(dout_port.lower(),bit,check))
|
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|
|
@ -205,17 +241,17 @@ class functional(simulation):
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self.v_high)
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return (0, error)
|
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|
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self.read_check.append([sp_read_value, dout_port, eo_period, check])
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self.read_results.append([sp_read_value, dout_port, eo_period, check])
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return (1, "SUCCESS")
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|
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def check_stim_results(self):
|
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for i in range(len(self.write_check)):
|
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if self.write_check[i][0] != self.read_check[i][0]:
|
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error = "FAILED: {0} value {1} does not match written value {2} read during cycle {3} at time {4}n".format(self.read_check[i][1],
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for i in range(len(self.read_check)):
|
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if self.read_check[i][0] != self.read_results[i][0]:
|
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error = "FAILED: {0} value {1} does not match written value {2} read during cycle {3} at time {4}n".format(self.read_results[i][1],
|
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self.read_results[i][0],
|
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self.read_check[i][0],
|
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self.write_check[i][0],
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||||
int((self.read_check[i][2]-self.period)/self.period),
|
||||
self.read_check[i][2])
|
||||
int((self.read_results[i][2]-self.period)/self.period),
|
||||
self.read_results[i][2])
|
||||
return(0, error)
|
||||
return(1, "SUCCESS")
|
||||
|
||||
|
|
@ -359,7 +395,7 @@ class functional(simulation):
|
|||
|
||||
# Generate dout value measurements
|
||||
self.sf.write("\n * Generation of dout measurements\n")
|
||||
for (word, dout_port, eo_period, check) in self.write_check:
|
||||
for (word, dout_port, eo_period, check) in self.read_check:
|
||||
t_intital = eo_period - 0.01*self.period
|
||||
t_final = eo_period + 0.01*self.period
|
||||
for bit in range(self.word_size):
|
||||
|
|
|
|||
|
|
@ -60,8 +60,10 @@ class simulation():
|
|||
port_info=(len(self.all_ports),self.write_ports,self.read_ports),
|
||||
abits=self.addr_size,
|
||||
dbits=self.word_size)
|
||||
debug.check(len(self.sram.pins) == len(self.pins), "Number of pins generated for characterization \
|
||||
do match pins of SRAM\nsram.pins = {0}\npin_names = {1}".format(self.sram.pins,self.pins))
|
||||
debug.check(len(self.sram.pins) == len(self.pins),
|
||||
"Number of pins generated for characterization \
|
||||
do match pins of SRAM\nsram.pins = {0}\npin_names = {1}".format(self.sram.pins,
|
||||
self.pins))
|
||||
#This is TODO once multiport control has been finalized.
|
||||
#self.control_name = "CSB"
|
||||
|
||||
|
|
@ -71,13 +73,18 @@ class simulation():
|
|||
self.t_current = 0
|
||||
|
||||
# control signals: only one cs_b for entire multiported sram, one we_b for each write port
|
||||
self.csb_values = [[] for port in self.all_ports]
|
||||
self.web_values = [[] for port in self.readwrite_ports]
|
||||
|
||||
# Three dimensional list to handle each addr and data bits for wach port over the number of checks
|
||||
self.addr_values = [[[] for bit in range(self.addr_size)] for port in self.all_ports]
|
||||
self.data_values = [[[] for bit in range(self.word_size)] for port in self.write_ports]
|
||||
self.wmask_values = [[[] for bit in range(self.num_wmasks)] for port in self.write_ports]
|
||||
self.csb_values = {port:[] for port in self.all_ports}
|
||||
self.web_values = {port:[] for port in self.readwrite_ports}
|
||||
|
||||
# Raw values added as a bit vector
|
||||
self.addr_value = {port:[] for port in self.all_ports}
|
||||
self.data_value = {port:[] for port in self.write_ports}
|
||||
self.wmask_value = {port:[] for port in self.write_ports}
|
||||
|
||||
# Three dimensional list to handle each addr and data bits for each port over the number of checks
|
||||
self.addr_values = {port:[[] for bit in range(self.addr_size)] for port in self.all_ports}
|
||||
self.data_values = {port:[[] for bit in range(self.word_size)] for port in self.write_ports}
|
||||
self.wmask_values = {port:[[] for bit in range(self.num_wmasks)] for port in self.write_ports}
|
||||
|
||||
# For generating comments in SPICE stimulus
|
||||
self.cycle_comments = []
|
||||
|
|
@ -105,7 +112,8 @@ class simulation():
|
|||
def add_data(self, data, port):
|
||||
""" Add the array of data values """
|
||||
debug.check(len(data)==self.word_size, "Invalid data word size.")
|
||||
|
||||
|
||||
self.data_value[port].append(data)
|
||||
bit = self.word_size - 1
|
||||
for c in data:
|
||||
if c=="0":
|
||||
|
|
@ -116,10 +124,12 @@ class simulation():
|
|||
debug.error("Non-binary data string",1)
|
||||
bit -= 1
|
||||
|
||||
|
||||
def add_address(self, address, port):
|
||||
""" Add the array of address values """
|
||||
debug.check(len(address)==self.addr_size, "Invalid address size.")
|
||||
|
||||
self.addr_value[port].append(address)
|
||||
bit = self.addr_size - 1
|
||||
for c in address:
|
||||
if c=="0":
|
||||
|
|
@ -130,10 +140,12 @@ class simulation():
|
|||
debug.error("Non-binary address string",1)
|
||||
bit -= 1
|
||||
|
||||
|
||||
def add_wmask(self, wmask, port):
|
||||
""" Add the array of address values """
|
||||
debug.check(len(wmask) == self.num_wmasks, "Invalid wmask size.")
|
||||
|
||||
self.wmask_value[port].append(wmask)
|
||||
bit = self.num_wmasks - 1
|
||||
for c in wmask:
|
||||
if c == "0":
|
||||
|
|
@ -143,10 +155,13 @@ class simulation():
|
|||
else:
|
||||
debug.error("Non-binary wmask string", 1)
|
||||
bit -= 1
|
||||
|
||||
|
||||
|
||||
def add_write(self, comment, address, data, wmask, port):
|
||||
""" Add the control values for a write cycle. """
|
||||
debug.check(port in self.write_ports, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_ports))
|
||||
debug.check(port in self.write_ports,
|
||||
"Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port,
|
||||
self.write_ports))
|
||||
debug.info(2, comment)
|
||||
self.fn_cycle_comments.append(comment)
|
||||
self.append_cycle_comment(port, comment)
|
||||
|
|
@ -159,16 +174,16 @@ class simulation():
|
|||
self.add_address(address,port)
|
||||
self.add_wmask(wmask,port)
|
||||
|
||||
#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
|
||||
noop_data = "0"*self.word_size
|
||||
#Add noops to all other ports.
|
||||
for unselected_port in self.all_ports:
|
||||
if unselected_port != port:
|
||||
self.add_noop_one_port(address, noop_data, wmask, unselected_port)
|
||||
self.add_noop_one_port(unselected_port)
|
||||
|
||||
def add_read(self, comment, address, din_data, wmask, port):
|
||||
def add_read(self, comment, address, port):
|
||||
""" Add the control values for a read cycle. """
|
||||
debug.check(port in self.read_ports, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_ports))
|
||||
debug.check(port in self.read_ports,
|
||||
"Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port,
|
||||
self.read_ports))
|
||||
debug.info(2, comment)
|
||||
self.fn_cycle_comments.append(comment)
|
||||
self.append_cycle_comment(port, comment)
|
||||
|
|
@ -176,21 +191,26 @@ class simulation():
|
|||
self.cycle_times.append(self.t_current)
|
||||
self.t_current += self.period
|
||||
self.add_control_one_port(port, "read")
|
||||
|
||||
#If the port is also a readwrite then add data.
|
||||
if port in self.write_ports:
|
||||
self.add_data(din_data,port)
|
||||
self.add_wmask(wmask,port)
|
||||
self.add_address(address, port)
|
||||
|
||||
#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
|
||||
noop_data = "0"*self.word_size
|
||||
# If the port is also a readwrite then add
|
||||
# the same value as previous cycle
|
||||
if port in self.write_ports:
|
||||
try:
|
||||
self.add_data(self.data_value[port][-1], port)
|
||||
except:
|
||||
self.add_data("0"*self.word_size, port)
|
||||
try:
|
||||
self.add_wmask(self.wmask_value[port][-1], port)
|
||||
except:
|
||||
self.add_wmask("0"*self.num_wmasks, port)
|
||||
|
||||
#Add noops to all other ports.
|
||||
for unselected_port in self.all_ports:
|
||||
if unselected_port != port:
|
||||
self.add_noop_one_port(address, noop_data, wmask, unselected_port)
|
||||
self.add_noop_one_port(unselected_port)
|
||||
|
||||
def add_noop_all_ports(self, comment, address, data, wmask):
|
||||
def add_noop_all_ports(self, comment):
|
||||
""" Add the control values for a noop to all ports. """
|
||||
debug.info(2, comment)
|
||||
self.fn_cycle_comments.append(comment)
|
||||
|
|
@ -200,39 +220,64 @@ class simulation():
|
|||
self.t_current += self.period
|
||||
|
||||
for port in self.all_ports:
|
||||
self.add_noop_one_port(address, data, wmask, port)
|
||||
self.add_noop_one_port(port)
|
||||
|
||||
def add_write_one_port(self, comment, address, data, wmask, port):
|
||||
""" Add the control values for a write cycle. Does not increment the period. """
|
||||
debug.check(port in self.write_ports, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_ports))
|
||||
debug.check(port in self.write_ports,
|
||||
"Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port,
|
||||
self.write_ports))
|
||||
debug.info(2, comment)
|
||||
self.fn_cycle_comments.append(comment)
|
||||
|
||||
self.add_control_one_port(port, "write")
|
||||
self.add_data(data,port)
|
||||
self.add_address(address,port)
|
||||
self.add_wmask(wmask,port)
|
||||
self.add_data(data, port)
|
||||
self.add_address(address, port)
|
||||
self.add_wmask(wmask, port)
|
||||
|
||||
def add_read_one_port(self, comment, address, din_data, wmask, port):
|
||||
def add_read_one_port(self, comment, address, port):
|
||||
""" Add the control values for a read cycle. Does not increment the period. """
|
||||
debug.check(port in self.read_ports, "Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port, self.read_ports))
|
||||
debug.check(port in self.read_ports,
|
||||
"Cannot add read cycle to a write port. Port {0}, Read Ports {1}".format(port,
|
||||
self.read_ports))
|
||||
debug.info(2, comment)
|
||||
self.fn_cycle_comments.append(comment)
|
||||
|
||||
self.add_control_one_port(port, "read")
|
||||
#If the port is also a readwrite then add data.
|
||||
if port in self.write_ports:
|
||||
self.add_data(din_data,port)
|
||||
self.add_wmask(wmask,port)
|
||||
self.add_address(address, port)
|
||||
# If the port is also a readwrite then add
|
||||
# the same value as previous cycle
|
||||
if port in self.write_ports:
|
||||
try:
|
||||
self.add_data(self.data_value[port][-1], port)
|
||||
except:
|
||||
self.add_data("0"*self.word_size, port)
|
||||
try:
|
||||
self.add_wmask(self.wmask_value[port][-1], port)
|
||||
except:
|
||||
self.add_wmask("0"*self.num_wmasks, port)
|
||||
|
||||
|
||||
def add_noop_one_port(self, address, data, wmask, port):
|
||||
def add_noop_one_port(self, port):
|
||||
""" Add the control values for a noop to a single port. Does not increment the period. """
|
||||
self.add_control_one_port(port, "noop")
|
||||
|
||||
try:
|
||||
self.add_address(self.addr_value[port][-1], port)
|
||||
except:
|
||||
self.add_address("0"*self.addr_size, port)
|
||||
|
||||
# If the port is also a readwrite then add
|
||||
# the same value as previous cycle
|
||||
if port in self.write_ports:
|
||||
self.add_data(data,port)
|
||||
self.add_wmask(wmask,port)
|
||||
self.add_address(address, port)
|
||||
try:
|
||||
self.add_data(self.data_value[port][-1], port)
|
||||
except:
|
||||
self.add_data("0"*self.word_size, port)
|
||||
try:
|
||||
self.add_wmask(self.wmask_value[port][-1], port)
|
||||
except:
|
||||
self.add_wmask("0"*self.num_wmasks, port)
|
||||
|
||||
def append_cycle_comment(self, port, comment):
|
||||
"""Add comment to list to be printed in stimulus file"""
|
||||
|
|
@ -240,16 +285,16 @@ class simulation():
|
|||
time = "{0:.2f} ns:".format(self.t_current)
|
||||
time_spacing = len(time)+6
|
||||
self.cycle_comments.append("Cycle {0:<6d} Port {1:<6} {2:<{3}}: {4}".format(len(self.cycle_times),
|
||||
port,
|
||||
time,
|
||||
time_spacing,
|
||||
comment))
|
||||
port,
|
||||
time,
|
||||
time_spacing,
|
||||
comment))
|
||||
|
||||
def gen_cycle_comment(self, op, word, addr, wmask, port, t_current):
|
||||
if op == "noop":
|
||||
comment = "\tIdle during cycle {0} ({1}ns - {2}ns)".format(int(t_current/self.period),
|
||||
t_current,
|
||||
t_current+self.period)
|
||||
t_current,
|
||||
t_current+self.period)
|
||||
elif op == "write":
|
||||
comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
|
||||
addr,
|
||||
|
|
|
|||
|
|
@ -96,22 +96,6 @@ class stimuli():
|
|||
self.sf.write(".ENDS test_{0}\n\n".format(buffer_name))
|
||||
|
||||
|
||||
def inst_buffer(self, buffer_name, signal_list):
|
||||
""" Adds buffers to each top level signal that is in signal_list (only for sim purposes) """
|
||||
for signal in signal_list:
|
||||
self.sf.write("X{0}_buffer {0} {0}_buf {1} {2} test_{3}\n".format(signal,
|
||||
"test"+self.vdd_name,
|
||||
"test"+self.gnd_name,
|
||||
buffer_name))
|
||||
|
||||
|
||||
def inst_inverter(self, signal_list):
|
||||
""" Adds inv for each signal that needs its inverted version (only for sim purposes) """
|
||||
for signal in signal_list:
|
||||
self.sf.write("X{0}_inv {0} {0}_inv {1} {2} test_inv\n".format(signal,
|
||||
"test"+self.vdd_name,
|
||||
"test"+self.gnd_name))
|
||||
|
||||
|
||||
def gen_pulse(self, sig_name, v1, v2, offset, period, t_rise, t_fall):
|
||||
"""
|
||||
|
|
@ -276,9 +260,6 @@ class stimuli():
|
|||
""" Writes supply voltage statements """
|
||||
gnd_node_name = "0"
|
||||
self.sf.write("V{0} {0} {1} {2}\n".format(self.vdd_name, gnd_node_name, self.voltage))
|
||||
# This is for the test power supply
|
||||
self.sf.write("V{0} {0} {1} {2}\n".format("test"+self.vdd_name, gnd_node_name, self.voltage))
|
||||
self.sf.write("V{0} {0} {1} {2}\n".format("test"+self.gnd_name, gnd_node_name, 0.0))
|
||||
|
||||
#Adding a commented out supply for simulators where gnd and 0 are not global grounds.
|
||||
self.sf.write("\n*Nodes gnd and 0 are the same global ground node in ngspice/hspice/xa. Otherwise, this source may be needed.\n")
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ class control_logic(design.design):
|
|||
self.enable_delay_chain_resizing = False
|
||||
self.inv_parasitic_delay = logical_effort.logical_effort.pinv
|
||||
|
||||
#Determines how much larger the sen delay should be. Accounts for possible error in model.
|
||||
# Determines how much larger the sen delay should be. Accounts for possible error in model.
|
||||
self.wl_timing_tolerance = 1
|
||||
self.wl_stage_efforts = None
|
||||
self.sen_stage_efforts = None
|
||||
|
|
@ -201,7 +201,7 @@ class control_logic(design.design):
|
|||
|
||||
def get_heuristic_delay_chain_size(self):
|
||||
"""Use a basic heuristic to determine the size of the delay chain used for the Sense Amp Enable """
|
||||
#FIXME: The minimum was 2 fanout, now it will not pass DRC unless it is 3. Why?
|
||||
# FIXME: The minimum was 2 fanout, now it will not pass DRC unless it is 3. Why?
|
||||
delay_fanout = 3 # This can be anything >=3
|
||||
# Model poorly captures delay of the column mux. Be pessismistic for column mux
|
||||
if self.words_per_row >= 2:
|
||||
|
|
@ -209,8 +209,8 @@ class control_logic(design.design):
|
|||
else:
|
||||
delay_stages = 2
|
||||
|
||||
#Read ports have a shorter s_en delay. The model is not accurate enough to catch this difference
|
||||
#on certain sram configs.
|
||||
# Read ports have a shorter s_en delay. The model is not accurate enough to catch this difference
|
||||
# on certain sram configs.
|
||||
if self.port_type == "r":
|
||||
delay_stages+=2
|
||||
|
||||
|
|
@ -226,7 +226,7 @@ class control_logic(design.design):
|
|||
def does_sen_rise_fall_timing_match(self):
|
||||
"""Compare the relative rise/fall delays of the sense amp enable and wordline"""
|
||||
self.set_sen_wl_delays()
|
||||
#This is not necessarily more reliable than total delay in some cases.
|
||||
# This is not necessarily more reliable than total delay in some cases.
|
||||
if (self.wl_delay_rise*self.wl_timing_tolerance >= self.sen_delay_rise or
|
||||
self.wl_delay_fall*self.wl_timing_tolerance >= self.sen_delay_fall):
|
||||
return False
|
||||
|
|
@ -236,8 +236,9 @@ class control_logic(design.design):
|
|||
def does_sen_total_timing_match(self):
|
||||
"""Compare the total delays of the sense amp enable and wordline"""
|
||||
self.set_sen_wl_delays()
|
||||
#The sen delay must always be bigger than than the wl delay. This decides how much larger the sen delay must be before
|
||||
#a re-size is warranted.
|
||||
# The sen delay must always be bigger than than the wl
|
||||
# delay. This decides how much larger the sen delay must be
|
||||
# before a re-size is warranted.
|
||||
if self.wl_delay*self.wl_timing_tolerance >= self.sen_delay:
|
||||
return False
|
||||
else:
|
||||
|
|
@ -250,14 +251,14 @@ class control_logic(design.design):
|
|||
debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay))
|
||||
|
||||
delay_fanout = 3 # This can be anything >=2
|
||||
#The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each
|
||||
#inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value
|
||||
# The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each
|
||||
# inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value
|
||||
required_delay = self.wl_delay*self.wl_timing_tolerance - (self.sen_delay-previous_delay_chain_delay)
|
||||
debug.check(required_delay > 0, "Cannot size delay chain to have negative delay")
|
||||
delay_stages = ceil(required_delay/(delay_fanout+1+self.inv_parasitic_delay))
|
||||
if delay_stages%2 == 1: #force an even number of stages.
|
||||
delay_stages+=1
|
||||
#Fanout can be varied as well but is a little more complicated but potentially optimal.
|
||||
# Fanout can be varied as well but is a little more complicated but potentially optimal.
|
||||
debug.info(1, "Setting delay chain to {} stages with {} fanout to match {} delay".format(delay_stages, delay_fanout, required_delay))
|
||||
return (delay_stages, delay_fanout)
|
||||
|
||||
|
|
@ -268,16 +269,16 @@ class control_logic(design.design):
|
|||
debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay))
|
||||
|
||||
fanout_rise = fanout_fall = 2 # This can be anything >=2
|
||||
#The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each
|
||||
#inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value
|
||||
# The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each
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# inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value
|
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required_delay_fall = self.wl_delay_fall*self.wl_timing_tolerance - (self.sen_delay_fall-previous_delay_chain_delay/2)
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required_delay_rise = self.wl_delay_rise*self.wl_timing_tolerance - (self.sen_delay_rise-previous_delay_chain_delay/2)
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debug.info(2,"Required delays from chain: fall={}, rise={}".format(required_delay_fall,required_delay_rise))
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||||
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#If the fanout is different between rise/fall by this amount. Stage algorithm is made more pessimistic.
|
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# If the fanout is different between rise/fall by this amount. Stage algorithm is made more pessimistic.
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WARNING_FANOUT_DIFF = 5
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stages_close = False
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#The stages need to be equal (or at least a even number of stages with matching rise/fall delays)
|
||||
# The stages need to be equal (or at least a even number of stages with matching rise/fall delays)
|
||||
while True:
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||||
stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall,fanout_fall)
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stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise,fanout_rise)
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|
|
@ -294,8 +295,8 @@ class control_logic(design.design):
|
|||
fanout_rise = safe_fanout_rise
|
||||
fanout_fall = safe_fanout_fall
|
||||
break
|
||||
#There should also be a condition to make sure the fanout does not get too large.
|
||||
#Otherwise, increase the fanout of delay with the most stages, calculate new stages
|
||||
# There should also be a condition to make sure the fanout does not get too large.
|
||||
# Otherwise, increase the fanout of delay with the most stages, calculate new stages
|
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elif stages_fall>stages_rise:
|
||||
fanout_fall+=1
|
||||
else:
|
||||
|
|
@ -304,13 +305,13 @@ class control_logic(design.design):
|
|||
total_stages = max(stages_fall,stages_rise)*2
|
||||
debug.info(1, "New Delay chain: stages={}, fanout_rise={}, fanout_fall={}".format(total_stages, fanout_rise, fanout_fall))
|
||||
|
||||
#Creates interleaved fanout list of rise/fall delays. Assumes fall is the first stage.
|
||||
# Creates interleaved fanout list of rise/fall delays. Assumes fall is the first stage.
|
||||
stage_list = [fanout_fall if i%2==0 else fanout_rise for i in range(total_stages)]
|
||||
return stage_list
|
||||
|
||||
def calculate_stages_with_fixed_fanout(self, required_delay, fanout):
|
||||
from math import ceil
|
||||
#Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay
|
||||
# Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay
|
||||
if required_delay <= 3+self.inv_parasitic_delay: #3 is the minimum delay per stage (with pinv=0).
|
||||
return 1
|
||||
delay_stages = ceil(required_delay/(fanout+1+self.inv_parasitic_delay))
|
||||
|
|
@ -421,7 +422,7 @@ class control_logic(design.design):
|
|||
row += 1
|
||||
if (self.port_type == "rw") or (self.port_type == "w"):
|
||||
self.place_rbl_delay_row(row)
|
||||
row += 1
|
||||
row += 1
|
||||
if (self.port_type == "rw") or (self.port_type == "r"):
|
||||
self.place_sen_row(row)
|
||||
row += 1
|
||||
|
|
@ -462,6 +463,7 @@ class control_logic(design.design):
|
|||
""" Create the replica bitline """
|
||||
self.delay_inst=self.add_inst(name="delay_chain",
|
||||
mod=self.delay_chain)
|
||||
# rbl_bl_delay is asserted (1) when the bitline has been discharged
|
||||
self.connect_inst(["rbl_bl", "rbl_bl_delay", "vdd", "gnd"])
|
||||
|
||||
def place_delay(self,row):
|
||||
|
|
@ -612,6 +614,8 @@ class control_logic(design.design):
|
|||
def create_pen_row(self):
|
||||
self.p_en_bar_nand_inst=self.add_inst(name="nand_p_en_bar",
|
||||
mod=self.nand2)
|
||||
# We use the rbl_bl_delay here to ensure that the p_en is only asserted when the
|
||||
# bitlines have already been discharged. Otherwise, it is a combination loop.
|
||||
self.connect_inst(["gated_clk_buf", "rbl_bl_delay", "p_en_bar_unbuf", "vdd", "gnd"])
|
||||
|
||||
self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar",
|
||||
|
|
@ -646,6 +650,9 @@ class control_logic(design.design):
|
|||
# GATE FOR S_EN
|
||||
self.s_en_gate_inst = self.add_inst(name="buf_s_en_and",
|
||||
mod=self.sen_and3)
|
||||
# s_en is asserted in the second half of the cycle during a read.
|
||||
# we also must wait until the bitline has been discharged enough for proper sensing
|
||||
# hence we use rbl_bl_delay as well.
|
||||
self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
|
||||
|
||||
|
||||
|
|
@ -669,7 +676,6 @@ class control_logic(design.design):
|
|||
|
||||
self.connect_output(self.s_en_gate_inst, "Z", "s_en")
|
||||
|
||||
|
||||
def create_rbl_delay_row(self):
|
||||
|
||||
self.rbl_bl_delay_inv_inst = self.add_inst(name="rbl_bl_delay_inv",
|
||||
|
|
@ -696,7 +702,8 @@ class control_logic(design.design):
|
|||
|
||||
rbl_map = zip(["A"], ["rbl_bl_delay"])
|
||||
self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets)
|
||||
|
||||
|
||||
|
||||
def create_wen_row(self):
|
||||
|
||||
# input: we (or cs) output: w_en
|
||||
|
|
@ -709,6 +716,7 @@ class control_logic(design.design):
|
|||
# GATE THE W_EN
|
||||
self.w_en_gate_inst = self.add_inst(name="w_en_and",
|
||||
mod=self.wen_and)
|
||||
# Only drive the writes in the second half of the clock cycle during a write operation.
|
||||
self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"])
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -61,16 +61,16 @@ class timing_sram_test(openram_test):
|
|||
data.update(port_data[0])
|
||||
|
||||
if OPTS.tech_name == "freepdk45":
|
||||
golden_data = {'delay_hl': [0.2181231],
|
||||
'delay_lh': [0.2181231],
|
||||
'leakage_power': 0.0025453999999999997,
|
||||
'min_period': 0.781,
|
||||
'read0_power': [0.34664159999999994],
|
||||
'read1_power': [0.32656349999999995],
|
||||
'slew_hl': [0.21136519999999998],
|
||||
'slew_lh': [0.21136519999999998],
|
||||
'write0_power': [0.37980179999999997],
|
||||
'write1_power': [0.3532026]}
|
||||
golden_data = {'delay_hl': [0.2383338],
|
||||
'delay_lh': [0.2383338],
|
||||
'leakage_power': 0.0014532999999999998,
|
||||
'min_period': 0.898,
|
||||
'read0_power': [0.30059800000000003],
|
||||
'read1_power': [0.30061810000000005],
|
||||
'slew_hl': [0.25358420000000004],
|
||||
'slew_lh': [0.25358420000000004],
|
||||
'write0_power': [0.34616749999999996],
|
||||
'write1_power': [0.2792924]}
|
||||
elif OPTS.tech_name == "scn4m_subm":
|
||||
golden_data = {'delay_hl': [1.7445000000000002],
|
||||
'delay_lh': [1.7445000000000002],
|
||||
|
|
|
|||
Loading…
Reference in New Issue