mirror of https://github.com/VLSIDA/OpenRAM.git
Do not run tapless unit tests
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7dc33285a7
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9930b5f3f6
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@ -25,10 +25,10 @@ class pnand2_test(openram_test):
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tx = factory.create(module_type="pnand2", size=1)
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self.local_check(tx)
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debug.info(2, "Checking 2-input nand gate")
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tx = factory.create(module_type="pnand2", size=1, add_wells=False)
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# Only DRC because well contacts will fail LVS
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self.local_drc_check(tx)
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# debug.info(2, "Checking 2-input nand gate")
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# tx = factory.create(module_type="pnand2", size=1, add_wells=False)
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# # Only DRC because well contacts will fail LVS
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# self.local_drc_check(tx)
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globals.end_openram()
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@ -25,10 +25,10 @@ class pnand3_test(openram_test):
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tx = factory.create(module_type="pnand3", size=1)
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self.local_check(tx)
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debug.info(2, "Checking 3-input nand gate")
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tx = factory.create(module_type="pnand3", size=1, add_wells=False)
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# Only DRC because well contacts will fail LVS
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self.local_drc_check(tx)
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# debug.info(2, "Checking 3-input nand gate")
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# tx = factory.create(module_type="pnand3", size=1, add_wells=False)
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# # Only DRC because well contacts will fail LVS
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# self.local_drc_check(tx)
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globals.end_openram()
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