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Convert psram tests to only 2 port.

This commit is contained in:
Matt Guthaus 2019-07-18 14:49:54 -07:00
parent 9696401f34
commit a707c6fa50
4 changed files with 17 additions and 6 deletions
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8
compiler/tests/22_psram_1bank_2mux_func_test.py
View File

@ -15,18 +15,20 @@ from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_2mux_1rw_1r_1w_func_test, third port reads are broken?")
class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
class psram_1bank_2mux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 1
# This is a hack to reload the characterizer __init__ with the spice version

5
compiler/tests/22_psram_1bank_4mux_func_test.py
View File

@ -23,10 +23,13 @@ class psram_1bank_4mux_func_test(openram_test):
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 1
# This is a hack to reload the characterizer __init__ with the spice version

5
compiler/tests/22_psram_1bank_8mux_func_test.py
View File

@ -23,10 +23,13 @@ class psram_1bank_8mux_func_test(openram_test):
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 1
# This is a hack to reload the characterizer __init__ with the spice version

5
compiler/tests/22_psram_1bank_nomux_func_test.py
View File

@ -23,10 +23,13 @@ class psram_1bank_nomux_func_test(openram_test):
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 1
# This is a hack to reload the characterizer __init__ with the spice version