mirror of https://github.com/VLSIDA/OpenRAM.git
Added a condiitonal to only route wmask dff when there's a write size.
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@ -259,7 +259,8 @@ class sram_1bank(sram_base):
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self.route_col_addr_dff()
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self.route_data_dff()
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self.route_wmask_dff()
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if self.write_size is not None:
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self.route_wmask_dff()
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def route_clk(self):
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""" Route the clock network """
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@ -20,7 +20,7 @@ import debug
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class write_driver_test(openram_test):
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def runTest(self):
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globals.init("config_{0}".format(OPTS.tech_name))
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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# check write driver array for single port
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debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")
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